Browse Prior Art Database

Method for Large Board Engineering Changes and Repair

IP.com Disclosure Number: IPCOM000111475D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 99K

Publishing Venue

IBM

Related People

Bentlage, JR: AUTHOR [+4]

Abstract

Disclosed is a multi-functional interposer whose primary purpose is to offer a generic pattern of controlled-impedance printed circuit lines that can be programmed, as needed, for performing Engineering Changes (ECs) and repairs on multilayered printed circuit boards while still allowing large-enough contact pads for adequate connector alignment tolerances and the proper functioning of high-density-area array connectors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method for Large Board Engineering Changes and Repair

      Disclosed is a multi-functional interposer whose primary
purpose is to offer a generic pattern of controlled-impedance printed
circuit lines that can be programmed, as needed, for performing
Engineering Changes (ECs) and repairs on multilayered printed circuit
boards while still allowing large-enough contact pads for adequate
connector alignment tolerances and the proper functioning of
high-density-area array connectors.

      The interposer would most likely be built using a dielectric
material like Kapton* or Upilex**.  Fig. 1 shows an overall exploded
view of a typical assembly which includes the interposer, while Fig.
2 shows a cross-sectional view of the interposer, and Figs. 3A and 3B
show top views of the contact pads, vias, and buried EC lines.

      The multi-functional interposer has four layers of circuitry
each separated by a dielectric layer (Fig. 2).  The bottom-most layer
consists of a set of pads that are used to attach the interposer to a
mating set of pads on the surface of the board.  The next layer is a
series of parallel printed circuit lines.  The third layer consists
of a series of parallel printed circuit lines that are perpendicular
to the previous layer.  The top layer consists of a set of contact
pads, each containing a via, which are connected vertically to the
identical pattern of pads on the bottom-most layer.  The top layer
pads are used to contact the interposer to an area array connector.
The top layer has an additional series of small vias, each...