Browse Prior Art Database

Hierarchical Fault Model Generation from a Design Database

IP.com Disclosure Number: IPCOM000111487D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 6 page(s) / 151K

Publishing Venue

IBM

Related People

Dibrino, M: AUTHOR [+3]

Abstract

Disclosed is a hierarchical fault model generation technique based on circuit design data stored in a design database.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 34% of the total text.

Hierarchical Fault Model Generation from a Design Database

      Disclosed is a hierarchical fault model generation technique
based on circuit design data stored in a design database.

      Most circuit design systems available today use hierarchical
structure.  A circuit designer designs and simulates transistor level
circuits to produce basic books.  These basic design books are then
connected together to produce higher level structures.  In order to
generate appropriate fault models, it is necessary to develop a
technique to produce different level of fault models for test
generation purposes.

In this disclosure, a technique that generates hierarchical fault
models from a design database is described.

      Based on a design database, a program that scan through
schematics is used to generate a 'tree structure' describing the
following features of each book and each higher level macro:

1.  'Parent' and 'Child' of each book and each higher level macro.

2.  For each book (transistor level), and for the highest level
    macro, the input and output pins are identified.

An example output of tree structure is shown in Fig. 1.

                          Fig. 1

   Begin Tree.....

  NI3T2BTJ    (P)  NSL9T2CSJ

              (C)  $NO

              (I) B, B_, C, C_, R, A_, A, P_CHL_GND, RN

              (O) SUM, SUM_, CARRY, CARRY_

  NSL9T2CSJ   (P)  NY7J

              (C)  NI3T2BTJ

  NY7J        (P)   $NO

              (C)  NSL9T2CSJ

            (I) R<0:3>, RN<0:3>, P_CHL_GND, PS8_<0:32>, PS8<0:32>,
PS7_<0:32>,

                PS7<0:32>, PS6_<0:32>, PS6<0:32>, PS5_<0:32>,
PS5<0:32>,

                PS4_<0:32>, PS4<0:32>, PS3_<0:32>, PS3<0:32>,
PS2_<0:32>,

                PS2<0:32>, PS1_<0:32>, PS1<0:32>, PS0_<0:32>,
PS0<0:32>, CN6_,

                CN6, CN5_, CN5, CN4_, CN4, CN3_, CN3, CN2_, CN2,
CN1_, CN1

            (O) SUM_<0:32>, SUM<0:32>, CARRY_<0:32>, CARRY<0:32>

   End Tree.....

      In the above example, there are three level of hierarchies.
Circuit NI3T2BTJ is the lowest level with 'parent' NSL9T2CSJ and no
'child'.  Circuit NSL9T2CSJ is the next level with 'parent' NY7J and
'child' NI3T2BTJ.  Circuit NY7J is the top level circuit with no
'parent' and with 'child' NSL9T2CSJ.

      For fault model generation purpose, a hierarchy Level Lists is
generated as shown in below:

  LA01: (NI3T2BTJ)

  LA05: (NSL9T2CSJ)

  LA10: (NY7J)

Based on this hierarchy, a node-indexing method is used to assign a
number to each input and output pin.

For example, the lowest level circuit NI3T2BTJ schematics has an
input /output list shown in Fig. 2.

                          Fig. 2

MODEL NI3T2BTJ(A- A_- B- B_- C- CARRY- CARRY_- C_- P_CHL_GND- R- RN-
SUM- SUM_- VDD-GND) * Generated from circuit NI3T2BTJ.

 ...