Browse Prior Art Database

LARX/STCX Interlocks and Broadcast

IP.com Disclosure Number: IPCOM000111492D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Merkel, LJ: AUTHOR [+4]

Abstract

Disclosed is a way to implement the LARX and STCX instructions of the PowerPC* architecture on a multiple issue, pipelined processor.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

LARX/STCX Interlocks and Broadcast

      Disclosed is a way to implement the LARX and STCX
instructions of the PowerPC* architecture on a multiple issue,
pipelined processor.

      The PowerPC architecture defines the LARX (Load and Reserve)
and STCX (Store Conditional) instructions for building atomic storage
update primitives.  The LARX instruction creates a reservation for an
address associated with the LARX address, and this reservation is
required for a STCX to complete successfully.  The address is snooped
against all bus traffic the processor sees, and, if another processor
takes exclusive access to the address, the reservation is reset.  The
lack of reservation will then cause a subsequent STCX to execute
unsuccessfully.

      In a multiple issue, pipelined processor, the reservation must
exist until the instruction has been globally performed.  This will
happen in several places in the pipeline, depending on the
translation attributes, cache hit or miss, and other factors.
Therefore, interlocks are necessary in various places along the
pipeline to check for a valid reservation before the STCX is allowed
to complete.  A standard pipeline with execute and write back stages,
an on-chip cache, and memory queueing below the cache is the model
for this processor.  The next two paragraphs describe one way of
providing these interlocks.

      The first set of interlocks are execution interlocks.  There
are four of these.  The first execution interlock is at the execute
state:  If the reservation bit is not set when the STCX is executed,
no request is passed to the cache.  This removes the storage portion
of the operation from the pipeline, allowing only the condition
register update to occur.  The second execution interlock is at the
cache access point:  If the address is exclusively owned, the
reservation bit is checked again before the cache is written.  If the
r...