Browse Prior Art Database

Character Parity and Framing Error Marking in a Direct Memory Access Environment

IP.com Disclosure Number: IPCOM000111512D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 153K

Publishing Venue

IBM

Related People

Clausen, TL: AUTHOR [+3]

Abstract

This article describes a method for marking blocks of character data received asynchronously into an I/O processor (IOP) and stored into processor memory via Direct Memory Access (DMA) hardware as blocks of data either received with errors (parity or framing errors) or without errors. The IOP passes data it receives on to a main (host) processor for use by an application program or the operating system. Any error data detected by the IOP must be distinguished from good data before passing it on to the main processor.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 34% of the total text.

Character Parity and Framing Error Marking in a Direct Memory Access
Environment

      This article describes a method for marking blocks of character
data received asynchronously into an I/O processor (IOP) and stored
into processor memory via Direct Memory Access (DMA) hardware as
blocks of data either received with errors (parity or framing errors)
or without errors.  The IOP passes data it receives on to a main
(host) processor for use by an application program or the operating
system.  Any error data detected by the IOP must be distinguished
from good data before passing it on to the main processor.

      The method described is specific to an IOP having certain
functional characteristics.  The characteristics are:

o   The IOP supports multiple ports via which asynchronous devices
    (e.g., ASCII displays or printers) can be attached.

o   The port hardware has the capability of receiving character data
    in a Direct Memory Access (DMA) mode.  In this mode, the port
    hardware takes care of moving each asynchronously received
    character from a port receiver register into a DMA buffer space
    (in IOP memory).  The microcode within the IOP thus does not read
    in each individual received character, and, instead, processes
    received data from within the DMA buffer at its convenience.

o   Each port on which data is received has two receive DMA buffer
    offset pointers associated with it.  A receive DMA buffer head
    offset pointer indicates the buffer location at which the next
    character received from the device will be placed by the DMA
    hardware, and a receive DMA buffer tail offset pointer indicates
    the location of the next character in the buffer which the code
    needs to process.  The Figure illustrates the relative locations
    of the head and tail offset pointers for a receive DMA buffer
    empty condition and for a condition in which data has been
    received into the buffer but has not yet been processed by the
    code.

o   Each port also has a status register indicating various
    conditions on the port.  Among the conditions indicated are
    several providing status on characters being received:

    -   Byte received -- activated when a character is received into
        the receiver register.

    -   Parity error -- activated when a parity error is detected on
        a received character.

    -   Framing error -- activated when a framing error is detected
        on a received character.

o   Each status condition described in the previous item is tied to a
    processor interrupt.  The interrupt associated with each can be
    individually enabled or disabled.  When an interrupt condition
    occurs, a general interrupt service procedure runs to process all
    active status conditions on each port.

o   The DMA hardware continues placing asynchronously recei...