Browse Prior Art Database

Superscalar Processor Architecture Using Flexible Execution Unit

IP.com Disclosure Number: IPCOM000111521D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 128K

Publishing Venue

IBM

Related People

Alpert, AI: AUTHOR [+4]

Abstract

Disclosed are mechanisms for constructing a processor execution unit which increases efficiency of processors executing more than one instruction simultaneously.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Superscalar Processor Architecture Using Flexible Execution Unit

      Disclosed are mechanisms for constructing a processor execution
unit which increases efficiency of processors executing more than one
instruction simultaneously.

Flexible Single Execution Unit

      At the time of an instruction decode (ID), the instruction
execution requirements are known.  The ID phase determines what types
and how many of each type of execution (EX) subunits (adders,
shifters, etc.) are required to execute each particular instruction.
This determination can be done for several instructions in parallel.
Once that information is known, allocation of subunits can be
performed not for a single instruction but for as many of them as can
fit in the set of the EX subunits that is available.  This
information is passed to the EX unit and it establishes appropriate
fences (boundaries) within its logic and subdivides itself for
executing several instructions in parallel.

      For example, consider an EX unit that has four adders, four
shifters, two multipliers, two comparators, and two logical subunits
(AND/OR/XOR -- logical AND, logical OR, logical exclusive OR).  A
fixed-point binary ADD instruction requires one adder.  A
floating-point MULTIPLY instruction requires one multiplier for
mantissas and one adder for exponents.  A LR instruction requires
none of the components (register transfer).  A COMPARE instruction
requires one comparator.  A logical AND instruction requires one
logical subunit.  All of these can be done in parallel by allocating
the appropriate subunits from the set available in the EX unit.

      In the example in Fig. 3, N+i denote instructions in the
incoming instruction stream, and Ti denote time quanta (successive
clics).  IA, IF, ID, OA, OF, EX, and CR denote the instruction
execution phases -- instruction address determination, instruction
fetc...