Browse Prior Art Database

Programmable Delay Line

IP.com Disclosure Number: IPCOM000111545D
Original Publication Date: 1994-Mar-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 83K

Publishing Venue

IBM

Related People

Goetschel, CJ: AUTHOR [+8]

Abstract

A programmable delay line is disclosed. The programmable delay line is used to provide a write precompensation function for a hard disk drive.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Programmable Delay Line

      A programmable delay line is disclosed.  The programmable delay
line is used to provide a write precompensation function for a hard
disk drive.

      The programmable delay line is shown in Fig. 1.  This topology
uses a string of N delay cells connected in series.  The output of
each delay cell is also connected to the inputs of an N:1 multiplexer
(mux).  The output of the N:1 multiplexer is a SHIFTED CLOCK signal.
This SHIFTED CLOCK signal is shifted in time with respect to the
REFERENCE CLOCK signal.  The REFERENCE CLOCK signal comes from a
dummy multiplexer that is connected to the INPUT CLOCK signal.  The
dummy multiplexer has the same amount of delay as the N:1
multiplexer.  Thus the only difference between the SHIFTED CLOCK and
the REFERENCE CLOCK signals is the number of delay cells selected by
the N:1 multiplexer.  The N:1 multiplexer is controlled by a CMOS
decoder.

      The circuit schematic for the fixed delay cell used in the
programmable delay line is shown in Fig. 2.  The delay cell consists
of an NPN differential pair (Q1 and Q2) that have PFETs (T1 and T2)
operating in their linear region for pull-up resistors.  The constant
delay through this cell is maintained by adjusting the bias current
(Ibias) to compensate for parasitic capacitance variations from
processing.  The operational amplifier in the swing reference circuit
is used to maintain a constant voltage swing in the delay cell
regardless of the...