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Multiple Clock Generator Circuit Invention

IP.com Disclosure Number: IPCOM000111644D
Original Publication Date: 1994-Mar-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 6 page(s) / 116K

Publishing Venue

IBM

Related People

Clark, RA: AUTHOR [+2]

Abstract

The principle purpose of &mcgc. is to provide free running clocks. Each clock has the same period, however the phase, duty cycle and delay of each clock is completely programmable. This circuit was implemented in Motorolas ECLinPS technology. The circuit consists of 3 main portions. They are:

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Multiple Clock Generator Circuit Invention

      The principle purpose of &mcgc.  is to provide free running
clocks.  Each clock has the same period, however the phase, duty
cycle and delay of each clock is completely programmable.  This
circuit was implemented in Motorolas ECLinPS technology.  The circuit
consists of 3 main portions.  They are:

1.  The tapped delay / redrive circuit.

2.  The individual clock circuits.

3.  The self test circuit.

      The Tapped Delay / Redrive circuit takes an input clock (with
50% duty), creates 0, 2, 4, 6, 8, 10, 12, and 14 nsec delayed
versions of it, then redrives each of these delayed taps out to 8
individual clock circuits.  The &mcgc.  contains 2 of these tapped
delay / redrive circuits, refered to as channels A and B.

      There can be either 1 or 2 input clocks.  The two 2 to 1
multiplexers on the inputs allow the channels to be driven from a
common source or independently.

      The 16 individual clock circuits each have programmable delay,
phase and duty cycle.  With a fine delay resolution of 20
picoseconds, the edge placement is extremely precise.  The clocks are
distributed on 50 ohm coaxial cable in differential ECLinPS
(trademark of Motorola).

      The self test circuit is made up of two 16 to 1 multiplexers.
The outputs of these muxes are driven off the card on two coaxial
cables.  These cables can be plugged into either a digital scope or a
counter/timer to determine the programmed accuracy of any clock.
Functional Areas

Tapped Delay / Redrive Circuit

      The tapped delay / redrive circuit is depicted in Fig. 2.  The
circuit is broken into two channels, A and B. Each channel drives 8
clock circuits.  Two 2 to 1 multiplexers decide which of the two
possible sources will drive each channel.  The signals +INa and -INa
are terminated 50 ohms to ground.  These inputs are intended to be
driven by a Hewlett Packard 500 MHz programmable pulse generator.
The signals +INb and -INb...