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Fuse Book Offering Redundancy Test Immediately

IP.com Disclosure Number: IPCOM000111646D
Original Publication Date: 1994-Mar-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 141K

Publishing Venue

IBM

Related People

Verwegen, P: AUTHOR

Abstract

This article describes an advanced design of a fuse book. It contains a transistor in series with the actual fuse, offering the possibility to 'simulate' a blown fuse. Normally, a wafer is tested first, the fixable chips are then fused, followed by a retest of the whole wafer. The advanced fuse book allows testing fixable arrays' redundancy immediately at first contact. Another feature of the design is the possibility to gate off a DC current flow through the fuse book, allowing a good Idd test of the chip.

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Fuse Book Offering Redundancy Test Immediately

      This article describes an advanced design of a fuse book.  It
contains a transistor in series with the actual fuse, offering the
possibility to 'simulate' a blown fuse.  Normally, a wafer is tested
first, the fixable chips are then fused, followed by a retest of the
whole wafer.  The advanced fuse book allows testing fixable arrays'
redundancy immediately at first contact.  Another feature of the
design is the possibility to gate off a DC current flow through the
fuse book, allowing a good Idd test of the chip.

Introduction

      Large arrays, either as standalone memory chips or embedded on
logic chips, contain redundancy to prevent the chips from being
thrown away in case a test is not completely successful.  At first
test, the (potential) fixable chips are identified.  Redundant
word-lines of the array are enabled, bad word-lines at the same time
disabled by blowing one or more fuses by laser light.  To make sure
that after fusing the circuitry functions completely correct, a
retest of the chip must be carried out.  This means double work load
and extra risks because the wafer must be tested, and, therefore,
contacted twice.  It would be a major advantage testing the
redundancy immediately at first contact as soon as the test result
shows that the chip can be fixed by fuse blow.

      Fig. 1 shows the design of a typical fuse book in CMOS
technology.  When the fuse is intact, the output of the right
inverter is logical 0.  When the fuse is blown, the output of the
first inverter stage is allowed to go down, forcing the output of the
second inverter to logical 1.

      The signal from the fuse book is fed to the redundant address
decoder.  Another input of this decoder is the enable line, which
also connects to a fuse with inverter stages.  In order to test (and
later use) the redundant address decoder and the redundant word-line
the 'Enable Address Decoder'-fuse must be blown.  The other fuses
determine which bad word-line is to be replaced.  Obvious is a DC
current flow through the fuse and the NFET of the first inverter
(when the fuse is intact).  This makes a chip Idd test unreliable.

Advanced Fuse Book Design

      Fig. 2 shows a method to overcome the test and DC current
problems.  It contains an extra PFET transistor in series with the
fuse.  Switching the transistor off will simulate a blown fuse and
simultaneously offer the possibility to gate off the DC current.

      As can be seen in Fig. 2, every fuse circuit contains a latch.
The information in this latch will determine if a fuse is simulated
'intact' or 'blown'.  The Disable Latch can be reset to enable the
redundant address decoder.  The others are used to set the address of
the failing word line.

      The latches can be integrated into the fusebook and connected
with each other to form a scan chain.  The placement is no
constraint, however.  In fact they can be pla...