Browse Prior Art Database

Designing Flexibility into Hardwired Logic

IP.com Disclosure Number: IPCOM000111661D
Original Publication Date: 1994-Mar-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 134K

Publishing Venue

IBM

Related People

Check, MA: AUTHOR [+3]

Abstract

Disclosed is a technique for adding flexibility to a logic design which contains hardwired logic. The primary reason for using hardwired logic is to maximize performance, but this has the disadvantage of being rigid, and the hardware must be replaced whenever there is a design change. In some situations changes occur frequently, and it becomes very costly for the manufacturer to replace hardware with each change. This article outlines a solution to this problem and shows how to design logic that is hardwired for performance and flexible to change. The technique is to design the hardwired logic and then implement some programmable logic on the side for use whenever the design must change. Design changes are performed by switching out a portion of the hardwired logic and replacing it with programmable logic.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Designing Flexibility into Hardwired Logic

      Disclosed is a technique for adding flexibility to a logic
design which contains hardwired logic.  The primary reason for using
hardwired logic is to maximize performance, but this has the
disadvantage of being rigid, and the hardware must be replaced
whenever there is a design change.  In some situations changes occur
frequently, and it becomes very costly for the manufacturer to
replace hardware with each change.  This article outlines a solution
to this problem and shows how to design logic that is hardwired for
performance and flexible to change.  The technique is to design the
hardwired logic and then implement some programmable logic on the
side for use whenever the design must change.  Design changes are
performed by switching out a portion of the hardwired logic and
replacing it with programmable logic.  Since most changes are small,
the system remains mostly hardwired and the impact on performance is
usually negligible.

      As an application of this design technique, the focus will be
on the instruction decode logic of a central processor.  It is common
for architecture changes to occur after the hardware has been
released to the field.  By making an instruction decoder which is
partially programmable, the manufacturer can save a significant
amount of money on the cost of doing field upgrades for changes in
the instruction set.  A second advantage of using a partially
programmable decoder is its power as a debugging tool.  A more
detailed discussion follows.

Opcode Compare for Debugging

      Opcode compare is a tool for debugging problems in the central
processor.  It consists of a set of programmable opcode registers,
each with a control word.  The user has the ability to control the
way instructions decode and execute by writing values into the opcode
and control registers.  To modify the behavior of an instruction, the
opcode is written to one of the opcode registers and a control word
is also written.  Each time that opcode decodes, its hardwired
instruction characteristic is modified according to the value of the
control word.  Actions that can be controlled include disabling
multiple instructions per cycle decode, disabling decode until all
prior instructions complete (disable overlap), serialization and
switching execution between hardware and microcode elements.  Fig. 1
illustrates how to...