Browse Prior Art Database

Current-Mode Level Shifter with Off-Chip Driver

IP.com Disclosure Number: IPCOM000111701D
Original Publication Date: 1994-Mar-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 92K

Publishing Venue

IBM

Related People

Tretter, LL: AUTHOR

Abstract

Disclosed is a device that performs a level shift from one on-chip voltage range to another voltage range and drives the signal "off-chip". The method used to perform the level shift makes use of current-mode techniques which will provide for a robust circuit with respect to process variations and circuit component ranges.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Current-Mode Level Shifter with Off-Chip Driver

      Disclosed is a device that performs a level shift from one
on-chip voltage range to another voltage range and drives the signal
"off-chip".  The method used to perform the level shift makes use of
current-mode techniques which will provide for a robust circuit with
respect to process variations and circuit component ranges.

      This circuit uses "steered" current moving from one voltage
range, +5 volts and ground, to another voltage range, -5 volts and
ground, to accomplish the required level shift.  Because of this
"current-mode" technique, the circuit described can be easily
modified for use with any symmetrical power supply values to very low
values.  This means the same topology of circuit can be easily
"mapped" to new lower voltage technologies.

      Referring to the circuit diagram, the input A0 connects to PFET
device T0 and NFET device T2 which are connected to form a CMOS
inverter.  Unlike the NFET devices, the PFET devices in the Figure
have a fourth connection which represents the N-WELL.  This N-WELL,
for the case of T0, is connected to GND.  All of the PFET devices in
the figure have this fourth connection.  Depending on whether the
device is operating between -5 volts and ground or ground and +5
volts, the well connection will be connected to either ground or +5
volts.  This fourth connection is not shown on the NFET devices
because these devices all share a common substrate.  Input B0 is also
connected to an inverter formed by PFET device T12 and NFET device
T13.  The output of the T12/T13 inverter is connected to the gates of
PFET devices T14 and T15.  When B0 is a logic 1, 0 volts for this
example, the output of the T12/T13 inverter is a zero, -5 volts for
this example, which will turn on T14 and T15, allowing normal circuit
function.  When B0 is low, the output of inverter T12/T13 is high
which will turn off devices T14 and T15, not allowing any current
flow in either of the legs they are positioned in.  This input, B0,
is used to tri-state the output of the off-chip driver.  For the rest
of the circuit description assume that B0 input is high.

      The output of inverter T0/T2 inputs to gates of PFET device T4
and NFET device T5 which...