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Automated Method for Calculation of Off-Chip Driver Contention Effects

IP.com Disclosure Number: IPCOM000111741D
Original Publication Date: 1994-Mar-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 136K

Publishing Venue

IBM

Related People

Borkenhagen, JM: AUTHOR [+2]

Abstract

An automated method for including off-chip driver contention effects in the static timing verification process of digital logic design is disclosed. Periods of excessive driver current due to contention are measured and reported for reliability analysis. Contention periods are converted into delay adders and used as adjustments for driver delays in the static timing verification process.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 40% of the total text.

Automated Method for Calculation of Off-Chip Driver Contention Effects

      An automated method for including off-chip driver contention
effects in the static timing verification process of digital logic
design is disclosed.  Periods of excessive driver current due to
contention are measured and reported for reliability analysis.
Contention periods are converted into delay adders and used as
adjustments for driver delays in the static timing verification
process.

      Data and enabling signal arrival times at inputs of off-chip
drivers are calculated as part of the static timing verification
process.  Input arrival times for each driver on a net can be
combined with the electrical turn-on and turn-off delays of each
driver to determine reliability and delay contention values on nets
with multiple drivers.

      The electrical turn-on delay of a driver is defined as the time
from when the voltage level at the input of the driver crosses the
driver's switching threshold voltage until the output of the driver
sources or sinks current.  The electrical turn-off delay of a driver
is defined as the time from when the voltage level at the input to
the driver crosses the driver's switching threshold voltage until the
output of the driver stops sourcing or sinking current.

      Reliability contention is defined as the maximum period of time
two drivers are driving the same net at the same time.  This period
of time must be less than the limit defined by the chip technology in
order to maintain reliability.  In this disclosure, reliability
contention is calculated between each driver pair on a net by adding
the arrival time of the disabling signal at the input of the driver
getting off the net to the turn-off delay of that driver and
subtracting the sum of the arrival time of the enabling signal at the
input of the driver getting on the net and the turn-on delay of that
driver.  This is accomplished by using data already generated as part
of the static timing verification process along with a table of
driver types with their associated turn-on and turn-off delays.  The
time-of-flight delay of the interconnecting wire between the drivers
can be included in the calculation for additional accuracy.

      The previous words are summarized with the the following
equation.  Reliability contention values are calculated for rising
and falling transitions on a net.

REL_CONT_H = (AT_DIS + TURN_OFF_DEL_L) - (AT_EN + TURN_ON_DEL_H
+ WIRE_DEL)

REL_CONT_L = (AT_DIS + TURN_OFF_DEL_H) - (AT_EN + TURN_ON_DEL_L
+ WIRE_DEL)

  REL_CONT_H:      Reliability contention for driving net high

  REL_CONT_L:      Reliability contention for driving net high

  AT_DIS:       Arrival time of disabling signal at input of driver

  AT_EN:           Arrival time of enabling signal at input of driver

  TURN_OFF_DEL_H:  Turn-off delay when driver is holding net high

  TURN_OFF_DEL_L:  Turn-off delay when driver is holding...