Browse Prior Art Database

Power-On Self-Test Memory Configuration Algorithm for Invalid CMOS/ NVRAM

IP.com Disclosure Number: IPCOM000111757D
Original Publication Date: 1994-Mar-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 169K

Publishing Venue

IBM

Related People

Cronk, D: AUTHOR [+2]

Abstract

Disclosed is a method for enabling installed system memory according to an internal memory POST (Power-On Self-Test) configuration algorithm, when the POST memory configuration stored in non-volatile storage, such as CMOS/NVRAM, is determined to be invalid. The memory configuration is set in CMOS/NVRAM by the setup routines of the system reference diskette to reflect a current system configuration. This configuration is determined to be invalid, for example, if the battery powering CMOS/NVRAM is dead, if the memory configuration of the system has been changed, if a base memory failure has occurred, or if the CMOS/NVRAM checksums are invalid. If the POST memory configuration in CMOS/NVRAM is determined to be valid, the memory subsystem is programmed by POST according to values from CMOS/NVRAM.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 36% of the total text.

Power-On Self-Test Memory Configuration Algorithm for Invalid CMOS/
NVRAM

      Disclosed is a method for enabling installed system memory
according to an internal memory POST (Power-On Self-Test)
configuration algorithm, when the POST memory configuration stored in
non-volatile storage, such as CMOS/NVRAM, is determined to be
invalid.  The memory configuration is set in CMOS/NVRAM by the setup
routines of the system reference diskette to reflect a current system
configuration.  This configuration is determined to be invalid, for
example, if the battery powering CMOS/NVRAM is dead, if the memory
configuration of the system has been changed, if a base memory
failure has occurred, or if the CMOS/NVRAM checksums are invalid.  If
the POST memory configuration in CMOS/NVRAM is determined to be
valid, the memory subsystem is programmed by POST according to values
from CMOS/NVRAM.

      Prior systems have enabled all supported planar memory in the
system if CMOS/NVRAM was determined to be invalid.  This approach,
however, may cause potential conflicts with adapter system memory and
non-system memory.  An example of how memory conflict can occur is
found in considering a system with two 4MB (megabyte) SIMM (Surface
Inline Memory Module) banks also having a 1MB non-system memory area
configured at an address beginning at 15MB.  If this configuration is
altered by adding two 4MB SIMM banks, the POST memory algorithm
enables the first two SIMM banks, along with the new SIMM banks, to
form 16MB of contiguous system memory.  At this point, the non-system
memory area at 15MB is in conflict with the planar memory, with both
non-system and system memory enabled.

      Also, the configuration algorithm can become complex and is not
consistent from one system to another.  For example, some system
memory controllers require that SIMM banks must be enabled on certain
boundary values, such as on a boundary that is a multiple of the bank
size.

      The POST test for system memory begins with a memory enable
routine, which initializes the memory controller for the current
memory configuration.  There may be a base memory enable routine and
an extended memory enable routine.  Next, a base memory test routine
tests the base memory.  Then, a base memory recovery routine loops
through the base memory enable and base memory test routines until
functional base memory is found, or until no base memory remains.  If
no functional base memory is found, an error is displayed, and the
system is halted; otherwise, the next routine, for base memory
installation, clears base memory and sets up the required data areas.
Next, routines for extended memory size determination and for
extended memory test are executed.  Then, an extended memory error
processing routine displays errors for extended memory failures, and
a usable memory size calculation routine calculates the size of
usable memory and sets the CMOS/NVRAM parameters.

      The routine...