Browse Prior Art Database

5-Volt Signal Levels from 3-Volt Logic

IP.com Disclosure Number: IPCOM000111759D
Original Publication Date: 1994-Mar-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Hoffman, JA: AUTHOR

Abstract

This circuit takes advantage of the low voltage embodiment of the CMOS Cold Sparing Off-Chip Driver (OCD) previously disclosed in [1]. The OCD solves the problem of forward biasing the protect diodes to the 3-volt supply of the CMOS OCD connection. Similar OCDs that can use this technique are disclosed in [2]. This circuit can accept an external voltage signal greater than the 3-volt supply without damage when the OCD is disabled (i.e., output is in a high impedance state).

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5-Volt Signal Levels from 3-Volt Logic

      This circuit takes advantage of the low voltage embodiment of
the CMOS Cold Sparing Off-Chip Driver (OCD) previously disclosed in
[1].  The OCD solves the problem of forward biasing the protect
diodes to the 3-volt supply of the CMOS OCD connection.  Similar OCDs
that can use this technique are disclosed in [2].  This circuit can
accept an external voltage signal greater than the 3-volt supply
without damage when the OCD is disabled (i.e., output is in a high
impedance state).

The circuit shown in the Figure is composed of:

1.  An off-chip drive with a mechanism to prevent forward biasing
     of the protect and parasitic diodes.

2.  An external pull-up resistor to provide a 5-volt level when the
    OCD is disabled.

3.  A single NAND gets used to enable or disable the OCD.

4.  A "D" flip-flop.

Circuit Operation is as follows:

1.  When the signal labeled Data In is at a logical "0", the OCD is
    enabled via the NAND gate, and the output is a logical "0".

2.  When the Data In signal changes to a logical "1", the OCD is
    still enabled, and the output immediately rises to the 3-volt
    level, which is sufficient to provide a logical "1", but not
    sufficient to provide a full 5-volt signal.

3.  One clock cycle later, the D flip-flop transfers the data "1" to
    the NAND gate, effectively shutting off the OCD.

4.  The external pull-up resistor then pulls the signal to the 5-volt
    le...