Browse Prior Art Database

Test Pattern Generation for Circuits with Orthogonal Inputs

IP.com Disclosure Number: IPCOM000111771D
Original Publication Date: 1994-Mar-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 88K

Publishing Venue

IBM

Related People

Dibrino, M: AUTHOR [+5]

Abstract

Disclosed is a software modeling technique to generate test patterns for orthogonal inputs without adding extra circuitry.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Test Pattern Generation for Circuits with Orthogonal Inputs

      Disclosed is a software modeling technique to generate test
patterns for orthogonal inputs without adding extra circuitry.

      An orthogonal circuit is a circuit that only operates correctly
when one and only one input is high.  If more than one input is high,
this orthogonal circuit under test could either produce an
indeterminate state or result in a functional failure.  In system
operation, it is guaranteed that only one of the inputs can be high.

      For non-critical paths, it is recommended that designers should
add additional logic, such as priority logic, to ensure no
non-orthogonal condition occurs.  However, in many cases, the design
solution could be expensive.

      In this disclosure, a software modeling technique is invented
to guarantee 100% orthogonal test patterns to be generated by a
deterministic test generator.  This invention eliminates the need for
additional test circuitry that may result in additional delay,
hardware overhead and extra design time.

      Fig. 1 describes an example that two input signals, A and B,
have to be orthogonal.  Using a pseudo model depicted in Fig. 1, A'
and B' are the new inputs that fed the logic under test.  If either A
or B is 'zero', A' equals to A, and B' equal to B.  However, if A and
B are both 'ONE', the new input A' and B' will be a 'X'.  During the
test generation process, the illegal pattern will be rejected by the
test generator.  Notice that we do not 'throw away' a pattern and
reduce test coverage.  Instead, we force the test generator to
generate an orthogonal pattern.

      Fig. 2 shows the case of three inputs.  If only one input is
'ONE', the new inputs A', B' and C' are equal to the original inputs
A, B, and C respectively.  If more that...