Browse Prior Art Database

Real-Time CISC Architecture HW Emulator On A RISC Processor

IP.com Disclosure Number: IPCOM000111772D
Original Publication Date: 1994-Mar-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Fazel, M: AUTHOR [+2]

Abstract

A method for emulating a CISC architecture CPU is disclosed. This method utilizes a RISC architecture microprocessor in association with a CISC to RISC hardware translator.

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This is the abbreviated version, containing approximately 100% of the total text.

Real-Time CISC Architecture HW Emulator On A RISC Processor

      A method for emulating a CISC architecture CPU is disclosed.
This method utilizes a RISC architecture microprocessor in
association with a CISC to RISC hardware translator.

      In the Figure, the hardware translator resides between the RISC
subsystem and memory where the CISC macroinstructions reside.  The
function of the hardware translator is to return RISC instructions
that are generated from each CICS macroinstruction.  In essence, the
RISC microprocessor is acting as a microinstruction engine.

      For each RISC microprocessor instruction cache line refill
request, the hardware translator calculates the physical address of
the corresponding CISC macroinstruction in main memory.  After
fetching the CISC macroinstruction from memory it performs a table
lookup within the hardware translator's memory array based on the
CISC opcode.  This will point to a series of "canned" RISC
microinstructions that emulate the CISC macroinstruction.  These RISC
microinstructions are then "tailored" for the other components of the
CISC macroinstruction.  The completed RISC microinstructions are then
returned to the RISC subsystem to satisfy the instruction fetch.