Browse Prior Art Database

Fast, Expandable Multi-Word, Multi-Bit Magnitude Comparator

IP.com Disclosure Number: IPCOM000111779D
Original Publication Date: 1994-Mar-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+2]

Abstract

The digital logic disclosed in this article provides high speed magnitude analysis of multi-bit words. The circuit designates the word or words with the greatest magnitude and produces the value of that word. The comparator is expandable because the number of bits per word and number of words compared can both be varied. It is flexible due to the fact that the front end can be modified to accommodate any magnitude scheme including Binary , Binary Coded Decimal, EBCDIC, and ASCII. Finally, it is fast because only a few levels of gates are required. This magnitude comparator is ideal for a number of applications including high speed arbitration on multi-drop networks such as the Micro Channel* bus and Futurebus+.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 58% of the total text.

Fast, Expandable Multi-Word, Multi-Bit Magnitude Comparator

      The digital logic disclosed in this article provides high speed
magnitude analysis of multi-bit words.  The circuit designates the
word or words with the greatest magnitude and produces the value of
that word.  The comparator is expandable because the number of bits
per word and number of words compared can both be varied.  It is
flexible due to the fact that the front end can be modified to
accommodate any magnitude scheme including Binary , Binary Coded
Decimal, EBCDIC, and ASCII.  Finally, it is fast because only a few
levels of gates are required.  This magnitude comparator is ideal for
a number of applications including high speed arbitration on
multi-drop networks such as the Micro Channel* bus and Futurebus+.

      The comparator consists of two parts: the front-end illustrated
in Fig.  1, and the back-end shown in Fig. 2.  The front compares two
words, A and B, and determines which has the greatest magnitude.  The
back compares the results from multiple front-ends and produces the
word and the value of the word with the greatest magnitude.

      Fig. 1 is the front-end for an N-bit word and a Micro Channel*
arbitration, magnitude sequence, i.e., all zeroes is the highest
value.  If the front-end is changed to a circuit similar to the
"74LS85", the design would change to a multi-word, multi-bit per
word, Binary Coded Decimal, magnitude comparator.  The one-bit output
of the fron...