Browse Prior Art Database

High Speed Phase Compensated System Clock Generator

IP.com Disclosure Number: IPCOM000111791D
Original Publication Date: 1994-Mar-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Ouellette, RJ: AUTHOR

Abstract

Disclosed is a circuit which can be used to create a continuous high frequency clock in a test system which operates with a limited operating frequency and does not support the generation of a free running clock.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 60% of the total text.

High Speed Phase Compensated System Clock Generator

      Disclosed is a circuit which can be used to create a continuous
high frequency clock in a test system which operates with a limited
operating frequency and does not support the generation of a free
running clock.

      Many memory cards require a continuous high speed master system
clock in their operation.  When using a low cost commercially
available tester this clock can be difficult to generate.  These
testers will sometimes support a limited number of cycles and only
allow the user the ability to pulse each timing channel once per
cycle.  A tester with a minimum cycle time specification of 50ns
would be limited to 20MHz operation.

      In this new method, a circuit was developed to create a very
fast free running system clock which is initiated by a pulse and
re-synchronized to the tester at each cycle boundary.  The key design
feature was that given a cycle with period containing minimum
variance a clock can be created running at speeds of up to 160MHz.

      The duty cycle and period of the clock can be controlled by
setting the values of two programmable delays.  In the circuit
diagram, D1 is used to set the period and D2 is used to set the duty
cycle.  D1 must be programmed such that the round trip delay from the
Q output of the flipflop to it's CLK input is equal to the period of
the desired waveform.  D2 must be set such that the round trip delay
from the Q* output of the flipflo...