Browse Prior Art Database

Hardware-Driven Memory Bus Master

IP.com Disclosure Number: IPCOM000111813D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Saunders, DM: AUTHOR [+2]

Abstract

Disclosed is a logic Memory Bus Master that controls the writing of registers in a logic module which is attached to a local bus. The local bus is a transfer agent which passes address and data information to devices attached to the bus. Registers within these devices are normally written from a microprocessor which is also attached to the bus. In this disclosure the Memory Bus Master instructs the memory to write the registers within these devices and completes this operation significantly faster than possible from a microprocessor. This is done by reading both register addresses and register data from the memory onto the local bus and into the registers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 61% of the total text.

Hardware-Driven Memory Bus Master

      Disclosed is a logic Memory Bus Master that controls the
writing of registers in a logic module which is attached to a local
bus.  The local bus is a transfer agent which passes address and data
information to devices attached to the bus.  Registers within these
devices are normally written from a microprocessor which is also
attached to the bus.  In this disclosure the Memory Bus Master
instructs the memory to write the registers within these devices and
completes this operation significantly faster than possible from a
microprocessor.  This is done by reading both register addresses and
register data from the memory onto the local bus and into the
registers.

      The Figure shows a block diagram of the relevant system
components.  Module 1 contains internal registers 2 that control its
operation dependent on the bit settings.  The local bus 3 attached to
module 1 also connects to memory 4, and microprocessor 5.  The
Hardware-Driven Memory Bus Master 6 attaches to the memory address
bus 7.  Upon detection of certain events, the Hardware-Driven Memory
Bus Master arbitrates for control of the local bus.  Upon gaining
control of the local bus the Hardware-Driven Memory Bus Master forces
a memory starting address which points to a sequence of control words
previously set up by the microprocessor.  The control words are
actually a sequence of register address/register data for module 1.
The sequence can be as long as d...