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Bus Load Reduction in Disk Array Controller through the Use of Multicast Busing Techniques

IP.com Disclosure Number: IPCOM000111821D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Brady, JT: AUTHOR

Abstract

The advent of small form factor disks and numerous design improvements has made the use of disk arrays feasible. One of the key elements of making an array usable is to minimize the number of disk accesses for writes to less than the complete parity domain. The record to be updated must be read, the old parity record must be read, the new record must be written, and the new parity record must be written to accomplish a single record write. The use of fast write caching techniques minimizes the number of times this must happen and increases the number of such operations that can be performed on a disk per time interval. However, the use of the cache in an array introduces a problem of bus bandwidth.

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Bus Load Reduction in Disk Array Controller through the Use of Multicast
Busing Techniques

      The advent of small form factor disks and numerous design
improvements has made the use of disk arrays feasible.  One of the
key elements of making an array usable is to minimize the number of
disk accesses for writes to less than the complete parity domain.
The record to be updated must be read, the old parity record must be
read, the new record must be written, and the new parity record must
be written to accomplish a single record write.  The use of fast
write caching techniques minimizes the number of times this must
happen and increases the number of such operations that can be
performed on a disk per time interval.  However, the use of the cache
in an array introduces a problem of bus bandwidth.  In the case of
the write the data must be passed from the system interface to one
memory buffer, then to a second buffer (in a different power domain),
then to a parity calculation unit, and finally to the disk for
storage.  In the case of a bus servicing a 100 MB/sec HPPI interface
this would amount to a base of 400 MB/sec.  of bus traffic just for
the data written to the subsystem.  The read of the old data and
parity, depending on the write hit ratio to the parity domain, could
represent 200 MB/sec., and the write back of the parity another 100
MB/sec.  The peak bus load would be 700 MD/sec.

      The solution involves the use of a multicast bus permitting the
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