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Browse Prior Art Database

Simultaneous Source/Target Renaming of Multiple Instructions

IP.com Disclosure Number: IPCOM000111826D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 94K

Publishing Venue

IBM

Related People

Karim, FO: AUTHOR [+2]

Abstract

This article describes a method whereby a processor may execute several instructions simultaneously and in an arbitrary order. Super-scalar microprocessors obtain high instruction throughput through the use of multiple execution units. A typical super-scalar architecture such as the RISC System/6000* employs a branch, load/store, fixed-point, and floating-point execution units. Two instructions are fetched per cycle, but out-of-order execution is not allowed. Register renaming is performed only in the special case of floating-point loads. This allows a floating-point (FPU) instruction and a floating-point load instruction with the same destination to execute in parallel. Another processor based on the RISC System/6000 architecture employs a branch unit, two fixed-point units, and three floating-point units.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Simultaneous Source/Target Renaming of Multiple Instructions

      This article describes a method whereby a processor may execute
several instructions simultaneously and in an arbitrary order.
Super-scalar microprocessors obtain high instruction throughput
through the use of multiple execution units.  A typical super-scalar
architecture such as the RISC System/6000* employs a branch,
load/store, fixed-point, and floating-point execution units.  Two
instructions are fetched per cycle, but out-of-order execution is not
allowed.  Register renaming is performed only in the special case of
floating-point loads.  This allows a floating-point (FPU) instruction
and a floating-point load instruction with the same destination to
execute in parallel.  Another processor based on the RISC System/6000
architecture employs a branch unit, two fixed-point units, and three
floating-point units.  Four instructions are fetched per cycle, and
up to five instructions can be dispatched.  All units may operate in
parallel regardless of source/destination conflict, and instructions
may execute out of order.  This ability requires that all
instructions be renameable and that up to four be renamed per cycle.

      This renaming is based on rename tables which store the
physical addresses of target registers.  The processor used in this
example implements 56 physical general-purpose registers (GPRs) and
56 Floating-Point Registers (FPRs).  Architecturally, there are 32

GPRs and 32 FPRs.  Two 32-entry rename tables are used to hold the
physical addresses of renamed GPRs and FPRs (one for each).  The
figure shows a simplified dataflow for source and destination
renaming.  For this example, only fixed-point renaming will be
discussed (renaming for floating-point instructions is identical).
Instructions I0 - I3 are shown at the top of the diagram.  Each
instruction consists of a Destination (D), two Sources (S) and an
opcode (not shown).  The CVT (Collision Vector Table) block on the
left generates physical addresses of unused GPR locations which are
used to rename the architected destinations.  The Rename Table is a
four-write port, eight-read port register file which holds the
renamed (physical) destination addresses from previous cycles.

      As instructions (I0-I3) enter the rename logic, sources and
destinations are renamed to physical addresses.  These addresses are
used to form con...