Browse Prior Art Database

State Machine Access Facility

IP.com Disclosure Number: IPCOM000111837D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 163K

Publishing Venue

IBM

Related People

Bronson, TC: AUTHOR [+3]

Abstract

A mechanism for monitoring or suspending a state machine based on entering or leaving a specified state is disclosed. The mechanism also provides for execution in a single-state step mode or a single-cycle step mode.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 35% of the total text.

State Machine Access Facility

      A mechanism for monitoring or suspending a state machine based
on entering or leaving a specified state is disclosed.  The mechanism
also provides for execution in a single-state step mode or a
single-cycle step mode.

      This invention is used with VLSI chips that are programmed by
an associated microprocessor.  The invention provides the capability
to manipulate and monitor state machine activity in a diagnostic
mode, in a simulation environment, and, most importantly, in a
functional mode.

      In a diagnostic capacity, the invention can be used to stop a
state machine(s) upon detection of an error.  The diagnostic code can
then perform error isolation, prepare for retry, or reset the state
machine, as needed.

      During simulation, this invention allows verification of state
machine sequences that can be used on the actual hardware.

      Once the hardware is available to be tested, the state machine
access facility allows greater visibility into the chip without the
need to manipulate and interpret scan strings, change what is
happening in the chip, force a particular state change, or reset the
state machine.

      This invention allows the application of a microcode patch
during the appropriate state and return of control back to the
hardware when the bug has been successfully bypassed.

This invention is made up of logic that provides the following
capabilities to each of the state machines:

o   a state machine patching facility,

o   breakpoint detection when entering a designated state for the

    first time,

o   breakpoint detection when a designated state is exited,

o   single-state stepping,

o   single-cycle stepping, and

o   event monitoring.

The Figure shows a generalized (generic) view of the State Machine
Update and Compare Logic.  Consider the state machine to operate in
one of two modes, as defined below:

Normal Mode This mode is characterized by normal state machine
          execution according to the "next state" logic that is
          designed in the hardware.  Only the hardware is allowed to
          update the state machine in Normal Mode.

Suspend Mode This mode is characterized by state machine execution
          according to microprocessor code control.  Only the
          microcode can update the state machine in Suspend Mode.  It
          is the only time that the microcode is allowed to update
          the state machine.  Suspend Mode can be entered by the
          hardware when the hardware detects an event that has been
          preconditioned by the microcode (e.g., breakpoint
          detection) or by the hardware (e.g., illegal state/sequence
          detection), or it can be entered directly by a microcode
          set operation of a Suspend Mode latch.

      As long as the state machine is not in...