Browse Prior Art Database

Multi Byte Dataflow Techniques with Single Byte Controls

IP.com Disclosure Number: IPCOM000111871D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 8 page(s) / 312K

Publishing Venue

IBM

Related People

Bergey, AL: AUTHOR [+2]

Abstract

This invention is a series of techniques for improving performance on a DASD (Direct Access Storage Device) control unit. They involve speeding up a single-byte-wide data path by widening it to several bytes wide. However, both the architecture and the existing microcode, which must be re-used, continue to treat the datapath as if it were one byte wide. The hardware uses the techniques of this invention to give the microcode the illusion that it is working with a byte-wide data path. These techniques are:

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Multi Byte Dataflow Techniques with Single Byte Controls

      This invention is a series of techniques for improving
performance on a DASD (Direct Access Storage Device) control unit.
They involve speeding up a single-byte-wide data path by widening it
to several bytes wide.  However, both the architecture and the
existing microcode, which must be re-used, continue to treat the
datapath as if it were one byte wide.  The hardware uses the
techniques of this invention to give the microcode the illusion that
it is working with a byte-wide data path.  These techniques are:

1.  A structured implementation philosophy that demands that all
    controls be byte-oriented even though the data path can handle
    more than one byte at a time.

2.  A FIFO (First-In, First-Out) buffer design that is physically
    implemented as a multi byte wide array behaves as if it were only
    one byte wide.

3.  A prefetch technique that appears to be one byte wide to the
    architecture, but is really several bytes wide.

4.  An improved priority mechanism that allows greater buffer
    efficiency and prevents lockouts.

DATAFLOW - The data path is a large FIFO buffer through which data
travels between the device and the channel.  Microcode may access the
FIFO and modify the data as it travels through the FIFO.

      The Figure is a dataflow demonstrating the invention.  It is
implemented with the following components:

1.  Four byte wide RAM array.  All four bytes must be read or written
    simultaneously.

2.  Microprocessor.  The microprocessor has random access to the FIFO
    buffer, using BAP (defined below).

3.  Buffer In Pointer, BIP.  Used for automatic data transfer stores
    into the FIFO buffer.  This pointer addresses to the byte.
    Whenever data is stored into the buffer, this pointer is
    incremented by one, two, three, or four, depending upon the
    number of bytes stored.

4.  Buffer Out Pointer, BOP.  Similar to BIP, but used for automatic
    data transfer fetches from the FIFO buffer.  Also addresses to
    the byte, and is incremented by one, two, three or four,
    depending upon the number of bytes stored.

5.  Buffer ALU Pointer, BAP.  Similar to BIP and BOP, but used for
    random or sequential buffer access by the microprocessor.  For
    random buffer access, the microprocessor loads this pointer
    directly.  For sequential access, hardware automatically
    increments this pointer after each use.

6.  Buffer empty/full mechanism.  This mechanism uses either an
    up/down counter or a BIP/BOP subtract circuit to determine if the
    buffer is empty or full, or how close to empty or full it is.

7.  Incrementer for automatic data transfer Increments BIP or BOP by
    one, two, three or four after each store or fetch.

8.  BAP incrementer.  Increments BAP by one, two, three or four.

9.  Priority logic.  The storing logic, fetching lo...