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Shift/Load/Hold Buffer with Temporary Register to Reduce Input Loading

IP.com Disclosure Number: IPCOM000111876D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Hardell Jr, WR: AUTHOR

Abstract

This disclosure describes a means to control a First-In, First-Out (FIFO) buffer where the data must be transfered directly into a latch. The data also needs to be used directly from that latch's output. This method uses a temporary register so that there are only 2 loads on the input bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Shift/Load/Hold Buffer with Temporary Register to Reduce Input Loading

      This disclosure describes a means to control a First-In,
First-Out (FIFO) buffer where the data must be transfered directly
into a latch.  The data also needs to be used directly from that
latch's output.  This method uses a temporary register so that there
are only 2 loads on the input bus.

      In this method of queueing, most latches need 3 ports.  The 3
ports are the shift, load, and hold ports.  Figs. 1 and 2 show the
block diagram for a four-deep shift/load/hold buffer.  The latches
are connected in a chain with the shift ports.  New data can be
loaded into any of the latches.  Data from the queue always comes
from the same latch (Latch 0 in Fig. 1).  The control logic must know
how many of the latches have valid data.  This buffering method is
simple except for the case when data is loaded and unloaded on the
same cycle, especially when the buffer is partially filled.

      The Figs. also give the equations for controlling the 4-deep
queue.  These equations can be easily expanded to control deeper
queues.  If the 3-port latches use pass-gate multiplexers on their
inputs, then the multiplexer delay should be negligible.  The valid
bits (V0, V1a,V1b, V2, V3) can be generated by having an extra bit in
each of the latches and in the data input.  The extra bit in
"data_in" is set to '1', and the corresponding input on the ports
labeled "null" are set to '0'.  Then the...