Browse Prior Art Database

Rejection of Program Interrupts Generated by Out-of-Order, Speculative Instructions

IP.com Disclosure Number: IPCOM000111901D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Arasi, MS: AUTHOR [+3]

Abstract

A superscalar microprocessor which allows instructions to execute speculatively and out of order has multiple floating-point units, multiple fixed-point units, and multiple load/store units which can all be executing different instructions. The load/store units execute all of the instructions which can generate program interrupts; in other words the load/store units detect all of the program interrupts generated by the microprocessor. Please note that all program interrupts on the microprocessor are precise, which means the microprocessor will identify the exact instruction that generated the interrupt.

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Rejection of Program Interrupts Generated by Out-of-Order, Speculative
Instructions

      A superscalar microprocessor which allows instructions to
execute speculatively and out of order has multiple floating-point
units, multiple fixed-point units, and multiple load/store units
which can all be executing different instructions.  The load/store
units execute all of the instructions which can generate program
interrupts; in other words the load/store units detect all of the
program interrupts generated by the microprocessor.  Please note that
all program interrupts on the microprocessor are precise, which means
the microprocessor will identify the exact instruction that generated
the interrupt.

      When a load/store unit detects a program interrupt, the unit
suspends execution of that instruction and will not execute any
instructions following this particular instruction.  This allows all
of the resources being used by this program to be preserved.  The
load/store unit notifies the superscalar control unit (SSCU) that an
interrupt has been detected and waits until a reply is sent from the
SSCU.  The Figure shows the interface between the load/store unit and
the SSCU.

      The SSCU maintains the current state of the microprocessor.
The SSCU has a collection of Collision Vector Tables (CVTs) which
track each instruction currently being executed.  Each entry in the
CVT contains an instruction and information about that instruction
such as correct order of the instruction relative to other
instructions, whether the instruction is speculative or not, and
whether the instruction has completed or is still executing.

      Typically, when the SSCU is informed that an interrupt has been
generated, it identifies the exact instruction in the CVT which
caused t...