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Using a Temporary Buffer to Hold the Second Access to a DRAM that Allows the Early Release of RAS

IP.com Disclosure Number: IPCOM000111914D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 93K

Publishing Venue

IBM

Related People

Genz, RH: AUTHOR [+3]

Abstract

An interleaved memory subsystem that accesses an interleave more than once per request can release RAS early if data is ready early and the data can be held in a temporary buffer. Fig. 1 shows a block diagram for a four-way interleaved memory card. Fig. 2 shows a timing diagram for two 8 transfer reads from the memory card. In this example the second read is from a different page (different row address) in the DRAMs. This requires that RAS be raised and the RAS precharge time be satisfied. There is 1 dead cycle (no data on the memory bus) between the last (eighth) transfer of the first read request and the first transfer of the second request. There is 1 dead cycle because it takes longer than four cycles to get the first data for the second request after RAS is raised.

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Using a Temporary Buffer to Hold the Second Access to a DRAM that
Allows the Early Release of RAS

      An interleaved memory subsystem that accesses an interleave
more than once per request can release RAS early if data is ready
early and the data can be held in a temporary buffer.  Fig. 1 shows a
block diagram for a four-way interleaved memory card.  Fig. 2 shows a
timing diagram for two 8 transfer reads from the memory card.  In
this example the second read is from a different page (different row
address) in the DRAMs.  This requires that RAS be raised and the RAS
precharge time be satisfied.  There is 1 dead cycle (no data on the
memory bus) between the last (eighth) transfer of the first read
request and the first transfer of the second request.  There is 1
dead cycle because it takes longer than four cycles to get the first
data for the second request after RAS is raised.

      If RAS can be raised a cycle earlier, the dead cycle can be
eliminated.  RAS and CAS are held low 1 cycle longer than is required
to access D4, D5, D6, and D7.  D4, D5, D6, and D7 are valid for 2
cycles each.  The memory bus is not ready for D4 when it is first
valid because D3 is being put on the memory bus.  D4 is kept valid
for a second cycle by holding RAS and CAS low for an extra cycle.  If
D4-D7 are held in a temporary buffer until they are needed, then RAS
and CAS can be raised a cycle early.  Fig. 3 shows D4-D7 being held
in a temporary buffer until they are needed....