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Browse Prior Art Database

Common Chip Pairs

IP.com Disclosure Number: IPCOM000111962D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Aichelmann Jr, FJ: AUTHOR

Abstract

For conventional DRAM applications pairs of chips have been used to overcome gaps in transfer. This gapless transfer is achieved by providing a separate low order address between the "chip pairs". This proposal provides for a way of eliminating this additional low order address bus by incorporating special on chip logic.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Common Chip Pairs

      For conventional DRAM applications pairs of chips have been
used to overcome gaps in transfer.  This gapless transfer is achieved
by providing a separate low order address between the "chip pairs".
This proposal provides for a way of eliminating this additional low
order address bus by incorporating special on chip logic.

      Fig. 1 depicts the conventional chip pairs structure with
separate low order address buses.  Fig. 2 shows the elimination of
this bus with an address bus common to both chips.  Fig. 3 depists
the functional logic block diagram associated with incorporating this
separate addressing within the chip.  At RAS time, data is placed on
the Do bit position of the chip which results in setting a latch
which is used to personalize the low order CAS address at CAS time.
Fig. 4 depicts the input condition which personalizes this chip.