Browse Prior Art Database

Centralized Abist for Chips with Multiple Memory Macros

IP.com Disclosure Number: IPCOM000112075D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Rapoport, S: AUTHOR

Abstract

The disclosure shows how significant areas of silicon can be saved by implementing one centralized ABIST to test all the individual memory macros at AC speeds.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 73% of the total text.

Centralized Abist for Chips with Multiple Memory Macros

      The disclosure shows how significant areas of silicon can be
saved by implementing one centralized ABIST to test all the
individual memory macros at AC speeds.

      The disclosure solves this previous timing barrier by
introducing a pipeline level between the ABIST and each memory macro.
This allows the delay between the ABIST and each memory macro to be
one full cycle which is more than sufficient for propagating the self
test signals from the ABIST to each macro.  The result is that the
ABIST generates the self test signals to be applied to the memory
macros one cycle before they are actually applied to the memories.

      The Figure shows the new configuration which allows all the
ABISTs previously associated with each memory macro to be
consolidated into a single ABIST macro.  The ABIST CENTRAL is exactly
the same as the ABIST that was previously associated to the memory
macro with the largest address space among the n memory macros.  The
ABIST CENTRAL generates all the self-test data and the registers
labelled REG1 to REGN stock the data to be applied to the memory
macro on the following cycle.  The number of latches in each macro
corresponds to the number of self-test signals that communicated
between the ABIST and the memory in the previous configuration.

      Each memory keeps a separate data compression register and its
associated fail address register.  This is necessary due to...