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Address Breakpoint Generation for Both Cached and Non-Cached Accesses

IP.com Disclosure Number: IPCOM000112089D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Karim, FO: AUTHOR [+3]

Abstract

During the debug of a program a technique of setting data address breakpoints is often used to isolate to a section of the program that is failing. A method is described below which allows software to select a single address breakpoint on a non-cached access, select a single address breakpoint on a cached access, or select a range of addresses from 64 to 4096 words that will cause an address breakpoint on a cached access.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Address Breakpoint Generation for Both Cached and Non-Cached Accesses

       Fig. 1.  DABR with Non-Cached Address

      During the debug of a program a technique of setting data
address breakpoints is often used to isolate to a section of the
program that is failing.  A method is described below which allows
software to select a single address breakpoint on a non-cached
access, select a single address breakpoint on a cached access, or
select a range of addresses from 64 to 4096 words that will cause an
address breakpoint on a cached access.  This address breakpoint
design was developed for a superscalar microprocessor such that the
maximum real cacheable memory size is (2**30) bytes.  Also, this
superscalar microprocessor may access other devices off-chip, so all
Effective Addresses (EA) greater than or equal to (2**31) bytes are
non-cacheable.  In this disclosure || is used to describe fields
which are concatenated to each other.  For example, 010||111 is the
same as 010111.

      The Data Address Breakpoint Register (DABR) is a 32 bit
register which specifies the address of a word on which to generate a
breakpoint.  If the DABR contains a cacheable address, the DABR
contains both the target address and an address bit mask to be
applied to the EA in order to allow checking ranges of addresses.  If
the DABR contains a non-cacheable address, then only the target
address to be compared to the EA of the target instruction is in the
register.  Since a non-cacheable target address may require up to 32
bits, the address bit mask is not supported for non-cached storage
ac...