Browse Prior Art Database

DCache Status with Dual Load/Store Execution

IP.com Disclosure Number: IPCOM000112091D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 106K

Publishing Venue

IBM

Related People

Thatcher, L: AUTHOR

Abstract

A method for managing the DCache (Data Cache) status in processors with dual load/store units is disclosed. DCache status is calculated and managed for simultaneous execution of 2 load/store instruction.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 39% of the total text.

DCache Status with Dual Load/Store Execution

      A method for managing the DCache (Data Cache) status in
processors with dual load/store units is disclosed.  DCache status is
calculated and managed for simultaneous execution of 2 load/store
instruction.

      The described processor contains a FXU (Fixed Point Unit) with
dual load/store units.  The FXU can execute 2 load or store
operations per cycle.  The DCache, DTLB's (Data Translation Lookaside
Buffers), and GPR's (General Purpose Registers) are fully dual ported
to support this design.  The design calls the dual load/store units
Ports 0 and 1.  Port 0 is always the oldest operation and Port 1 the
newest.  Any combination of load/store operations can be executed on
the ports and Port 1 can be dependent on Port 0.  Port 1 dependent on
Port 0 means that the address on the ports are equal in at least the
DCache address and may be equal to the byte address.  With this
background a look at how DCache status is managed can be shown.

      The processor DCache status is maintained in a fully dual
ported registerfile.  There are 2 read and 2 write ports with all
writes bypassed to reads.  This gives the logical ordering of writes
before reads.  The DCache is a 256KB 4-way set associate cache with a
256b line.  The DCache is maintained as a store-in type design.  Fig.
1 shows the definition of the status word.  The timing for the DCache
status registerfile is illustrated in Fig. 2.  A typical pipeline
cycle is to first update and write the previous cycles status and
when read the current cycle's status.  So far the DCache status
structure is typical of a single load/store unit design expanded to a
dual unit.  However there are two very unique features to the dual
unit design.

      The first new feature can be seen in the dataflow diagram in
Fig. 3.  Here is shown the twist required to calculate status in Port
1 when the Port 1 is dependent on Port 0.  Fig. 4 shows the second
unique case where in Port 0 a DCache 'miss' is detected and in Port 1
a DCache 'hit' is detected.  This time again Port 1 is dependent on
Port 0 and Port 1 is the LRU selected for Port 0.  This creates a
real problem for to reload Port 0 into Port 1 would causes Port 1 to
'miss'.  Since this is a store-in DCache design if Port 1 required a
store-back it would be lost.  The reason for this is that reloads and
store-backs occur in a fixed sequence on the same port.  Here the
approach taken is to look at the next LRU selection and use it.  This
also provides some improvement in the Dcache 'hit' ratio giving a
looking ahead effect.

Fig. 2  DCache Status Word Definition

 Bits    0        5 6          13 14        17

        | LRU Bits | Change Bits | Valid Bits |

Notes:

 LRU Bits    : 6 bits are used to keep a 'true' LRU on a 4-way
                set associate DCache.

 Change Bits : 2 change bits are used per DCache line to mark...