Browse Prior Art Database

Verification of Logic Chips on Multicycle Busses

IP.com Disclosure Number: IPCOM000112127D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Schommer, PJ: AUTHOR

Abstract

Disclosed is a verification method for hardware logic which interfaces via Multicycle Busses. This method ensures that the hardware latches data off the bus during the correct cycle even though the data is on the bus for more than one cycle.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 99% of the total text.

Verification of Logic Chips on Multicycle Busses

      Disclosed is a verification method for hardware logic which
interfaces via Multicycle Busses.  This method ensures that the
hardware latches data off the bus during the correct cycle even
though the data is on the bus for more than one cycle.

      Chip verification environments in which a chip interface bus
runs at a clock cycle which is a multiple of the chip internal clock
cycle are exposed to the chip latching valid data off the bus during
an invalid cycle.  This could cause a logical timing miss which would
not be caught by other methods of verification.

      If you are using a simulator with greater than two value
simulation, then you can drive Bad Values (in our case we used X's)
on all cycles which would normally have valid data but should not be
latched by the chip.  This way, if the chip does latch during the
wrong cycle the bad data will propagate inside the chip and corrupt
simulation, thus detecting the error.

Note: In this example, Chip cycle 2 is the valid cycle to latch data
on.

                                 Chip       Chip

                                Cycle 1    Cycle 2

                               _____________________

                 DATA    ______|XXXXXXXXX|  Valid  |_________

                                    BUS CY...