Browse Prior Art Database

Extended Stream Data Procedure for the MICRO CHANNEL

IP.com Disclosure Number: IPCOM000112155D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+2]

Abstract

The Micro Channel* Architecture contains a high performance data transfer protocol called Streaming Data. With Streaming Data transfers, 100ns streaming data cycles are attainable. Described is a method which quadruples the Micro Channel performance by providing Extended Streaming Data transfers of 25ns. With the Extended Streaming Data procedure (and 64 bit data transfers) the peak Micro Channel bandwidth can be increased to 320 MB/sec.

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Extended Stream Data Procedure for the MICRO CHANNEL

      The Micro Channel* Architecture contains a high performance
data transfer protocol called Streaming Data.  With Streaming Data
transfers, 100ns streaming data cycles are attainable.  Described is
a method which quadruples the Micro Channel performance by providing
Extended Streaming Data transfers of 25ns.  With the Extended
Streaming Data procedure (and 64 bit data transfers) the peak Micro
Channel bandwidth can be increased to 320 MB/sec.

      The current Streaming Data (SD) protocol requires all SD
masters and slaves to provide/receive, DATA and CONTROL information
on a cycle by cycle basis.  This allows optimal flexibility by
allowing the masters and slaves to terminate/pace streaming on any
cycle.  The critical timings in the current SD protocol, however, are
in the transfer of CONTROL information on a cycle by cycle basis.  In
a single cycle, the master and slave must receive CONTROL information
and determine the data input of control latches so that the next
cycle contains the appropriate CONTROL information.  For example,
during a slave terminated sequence, the master, in a single cycle,
must receive the -SDR(0..1), determine the data input of the -S0,1
latches, -CMD latch, and the -SD STROBE latch, so that the next cycle
contains the correct CONTROL information.  However, the transfer of
DATA during the SD protocol is not timing critical.  Write DATA by a
master is not timing critical because the DATA and STROBE are tracked
out to the slave.  Read DATA by a master is not timing critical
because the master can track external delays and pipeline the DATA
back into the chip.  Thus, to achieve higher data rates during SD,
the limiting factor is the cycle by cycle transfer of CONTROL
information, not DATA.

      The Extended Streaming Data Procedure provides a mechanism by
which the higher data rates can be achi...