Browse Prior Art Database

Detector of Stuck Faults in Clocks

IP.com Disclosure Number: IPCOM000112157D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 182K

Publishing Venue

IBM

Related People

Bailey, JA: AUTHOR [+4]

Abstract

Disclosed is a circuit which verifies the presence of clock pulses. In the type of failure in digital circuits known as "stuck fault," the voltage level of a circuit node supposed to switch between digital "0" and "1" remains or is stuck at either level thus preventing the propagation of digital signals through the circuit. Stuck faults in clock circuits are obviously of a catastrophic nature and therefore it is very appealing to have a detector circuit capable of signaling the presence of a stuck fault in a clock circuit.

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Detector of Stuck Faults in Clocks

      Disclosed is a circuit which verifies the presence of clock
pulses.  In the type of failure in digital circuits known as "stuck
fault," the voltage level of a circuit node supposed to switch
between digital "0" and "1" remains or is stuck at either level thus
preventing the propagation of digital signals through the circuit.
Stuck faults in clock circuits are obviously of a catastrophic nature
and therefore it is very appealing to have a detector circuit capable
of signaling the presence of a stuck fault in a clock circuit.

      A block diagram of the proposed circuit to detect stuck faults
in clock circuits is shown in Fig.1 (a).  It consists of three
circuits: a clock transition detector, a comparator, and a driver.
In the Figure, the circuit schematic for the transition detector
using ideal components has been drawn within its block.  Its
operation is described next.

      The circuit for the clock transition detector consists of
capacitors C1 and C2 driven by the complement of the clock and
switches S1, S2, S3, and S4 that charge C2 and are driven by both
phases of the clock.  These switches are opened by the clock phases
shown in Fig. 1(a).  When the clock output is high or "1," S1 and S2
are opened and S3 and S4 are closed thereby isolating the charge Q2
and voltage V2 across C2 and discharging C1 to ground as illustrated
in Fig. 1(b).  When the clock output switches to low or "0," S1 and
S2 are closed while S3 and S4 are opened, thus forming the circuit in
Fig. 1(c).  There occurs a redistribution of Q2 and of the clock high
voltage level, VDD, between C1 and C2.  The steady state result of
these charge and voltage redistributions is an increase in V2 given
by

Delta V2 = left lbracket C1 over <(C1 + C2)> right rbracket (VDD -
              V2)      [1]

      According to Equation (1), each succesive value of V2 in Fig.
1(c) increases by a smaller DeltaV2 since (VDD - V2) is smaller for
each successive cycle.  This leads to an exponential growth of V2
towards VDD given by

V2 = (VDD) lbracket 1 - e sup <-t/tau>                    [2]
where tau is the time constant of the transition detector given by
tau = (C2/(f sub c C1))                                [3]
where f sub c is the clock frequency.  Comparison of this time
constant with the continuous response of an RC series network clearly
shows that, for a discrete response, the factor (1/f sub c C1)) is
the equivalent of the R of the continuous response.

      This circuit performs the function of a clock transition
detector because either V2 rises towards VDD if the clock is
oscillating or discharges towards zero through parasitic leakages of
real capacitors when the clock is stuck and the circuit remains in
either of the states in Figs. 1(b) or 1(c).

      To interface this detector with the digital system served by
the clock, a comparato...