Browse Prior Art Database

Cache and Snoop Hit Monitoring of a High-Performance RISC Microprocessor

IP.com Disclosure Number: IPCOM000112166D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Barrera, DD: AUTHOR [+2]

Abstract

Disclosed is a method of monitoring cache and snoop logic signals internal to a RISC microprocessor to facilitate debugging and performance verification of the processor.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Cache and Snoop Hit Monitoring of a High-Performance RISC Microprocessor

      Disclosed is a method of monitoring cache and snoop logic
signals internal to a RISC microprocessor to facilitate debugging and
performance verification of the processor.

      Today's high-performance RISC microprocessors frequently are
designed with large L1 caches with hardware bus snooping for
coherency checking.  Hardware debugging of systems incorporating such
processors proves to be quite a challenge.  The debug would most
likely be performed by monitoring activity on the I/O pins of the
chip (i.e., the memory bus).  With most data and instruction requests
being serviced by the L1 cache, trying to determine the state of the
processor is difficult.

      By adding two additional pins, a processor is able to monitor
cache and snoop activity inside the processor.  Some of the
information placed on these two pins can be: 1) The type of cache
operation being performed (e.g., load, store, or fetch), 2) cache
coherency state bits (MESI), 3) State bits for the snoop operation,
4) whether the operation is cacheable, non-cacheable, global, or
non-global, and 5) whether snoop hits have occurred.

      Which of the above information is placed on the two output pins
can be selected by a simple multiplexor mechanism controlled by
scan-only LSSD latches.