Browse Prior Art Database

Procedure and Design to Facilitate

IP.com Disclosure Number: IPCOM000112169D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Amos, RA: AUTHOR [+2]

Abstract

Very fast workstations and other machines incorporate wide data busses to convey data between processing elements and memory, I/O, or other processors. The very fastest incorporate central crossbar switching networks that allow for point to point interconnections for maximum electrical bandwidth. Because of chip I/O capabilities it is necessary to split this data bus into bundles, with the like bundle of each bus entering the switch section switched through the same crossbar switch chip. This interconnection may be of an asynchronous nature, but generally is not because of the need to reserve a bundle conductor to carry clocking information along with the data.

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Procedure and Design to Facilitate

      Very fast workstations and other machines incorporate wide data
busses to convey data between processing elements and memory, I/O, or
other processors.  The very fastest incorporate central crossbar
switching networks that allow for point to point interconnections for
maximum electrical bandwidth.  Because of chip I/O capabilities it is
necessary to split this data bus into bundles, with the like bundle
of each bus entering the switch section switched through the same
crossbar switch chip.  This interconnection may be of an asynchronous
nature, but generally is not because of the need to reserve a bundle
conductor to carry clocking information along with the data.
Normally great care is taken during system package design to get
accurate clocking information to each chip, so in an asynchronous
environment one knows the frequency of the incoming data, viewed from
the switch perspective, and needs to correct the phase.

      If one encodes clocking phase information using a line code
such as NRZ or NRZI then the data conveys the clocking information.
This encoding could be on one conductor of the bundle, and it would
be regenerated at the receiving end to strobe the data in the rest of
the bundle into a boundary register.  Techniques well understood by
logic designers then can be used to return the data into the
receiving chip synchronous clocking environment.

      NRZI is a "change-on-one" technique.  If B is 0 1 0...