Browse Prior Art Database

Display Mode Detection for Multimode Monitors

IP.com Disclosure Number: IPCOM000112184D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 102K

Publishing Venue

IBM

Related People

Johnston, I: AUTHOR [+3]

Abstract

Existing Multimode Monitor display mode detection systems find it difficult to resolve modes which are very close to each other in terms of frame and scan sync frequencies. The method disclosed permits a much finer mode resolution by counting pulses of a known duration during a measurement window.

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This is the abbreviated version, containing approximately 52% of the total text.

Display Mode Detection for Multimode Monitors

      Existing Multimode Monitor display mode detection systems find
it difficult to resolve modes which are very close to each other in
terms of frame and scan sync frequencies.  The method disclosed
permits a much finer mode resolution by counting pulses of a known
duration during a measurement window.

      Traditionally, Multimode Monitor sync line signals have been
integrated with respect to time such that a mainly high (active low)
signal will produce a logic "1" and a mainly low (active high) signal
will produce a logic "0".  Thus, by changing the sense of the sync
lines, the display has been able to resolve 4 distinct modes.  For
overscan displays, the overscan function has been indicated to the
display by a wide frame sync pulse.  Various solutions have been
proposed for the recognition of this condition e.g. the use of a
monostable to measure the sync pulse width in conjunction with the
above mentioned integrator.  Whilst this solution is adequate for
modes with wide variations between distinct modes, it is not
sufficient to resolve close modes (Table 1).

      Proposed is a scheme shown in the Figure to be used to resolve
individual modes.  For each of horizontal and vertical sync lines,
the signals are first optionally buffered to provide increased noise
immunity.  These signals are gated with a reference timebase and this
gated signal is used to clock an n-bit counter, where n is the number
of bits used in the counter for the desired count value.  For
increased resolution, it will be realised that a faster timebase may
be utilised, at the expense of a longer counter.  From the method of
gating, the upper counter counts the gated active high portion of the
sync pulse whilst the lower counter counts the gated active low
portion of the sync signal.  Assumed is that the display has within
it some control mechanism based on a microprocessor or similar device
which is capable of reading the sync counter values and using the
information contained to adjust the display operating conditions.
The control system in the display will read the values from each of
the counters and from these can calculate the frequency and duty
cycle of each of the horizontal and vertical sync lines.  Using this
information, mode resolution can be performed and the control system
of the display can take action to adjust the monitor to the correct
settings for the displayed image.

      Based on the information in Table 1, the following demonstrates
the effectiveness of this system in close mode resolution.

Mode Name     Line Rate     Frame Rate     Line Pulse     Frame Pulse

XGA           35520Hz       87.0Hz    ...