Browse Prior Art Database

Programmable Performance Monitor Apparatus for a Multi-Chip Super Scalar Processor

IP.com Disclosure Number: IPCOM000112197D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 8 page(s) / 322K

Publishing Venue

IBM

Related People

Hicks, DA: AUTHOR [+4]

Abstract

Performance monitor information provides vital information to study the performance characteristics of a computer as well as providing useful information for future computer design points. High speed super scalar architectures often require multiple chips to implement, and, contain many monitor points. This invention disclosure describes a flexible performance monitor scheme which allows software to control, monitor, and access many monitor points in a multichip super scalar computer.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 20% of the total text.

Programmable Performance Monitor Apparatus for a Multi-Chip Super
Scalar Processor

      Performance monitor information provides vital information to
study the performance characteristics of a computer as well as
providing useful information for future computer design points.  High
speed super scalar architectures often require multiple chips to
implement, and, contain many monitor points.  This invention
disclosure describes a flexible performance monitor scheme which
allows software to control, monitor, and access many monitor points
in a multichip super scalar computer.

The MMCR will be set to zero on power up.  Reading this register does
NOT change its content.  Bits 6 through 15 are reserved, and always
read as zeroes.  In order to maintain compatibility with future
implementations, software must NOT write nonzero values into bits 6
through 15.  The named fields have the following definitions.

DIS:   Disable counting undonditionally: This bit when set to a one,
causes the counters to stop counting unconditionally.  The counter
values are not changed, only suspended.

DP:   Disable counting when in privileged state: This bit when set to
a one, causes the counters to stop counting when MSR(PR) is set to a
zero.  The counter values are not changed, only suspended.

DU:   Disable counting when in problem state: This bit when set to a
one, causes the counters to stop counting when MSR(PM) is set to a
one.  The counter values are not changed, only suspended.

DMS:  Disable counting when PM is set: This bit when set to a one,
causes the counters to stop counting when MSR(PM) is set to a one.
The counter values are not changed, only suspended.

DMR:  Disable counting when MSR(PM) is clear: This bit when set to a
one, causes the counters to stop counting when MSR(PM) is set to a
one.  The counter values are not changed, only suspended.

SGA:  SCU Gets All: This bit when set to a one allows the SCU to
control all twenty two counters i.e., the SCU gets all of the
counters.  This bit over rides the FPU, FXU, ICU, and SCU source
event set selection.

FPU:  PMCR[16:19], 4-bit code selecting FPU surce event set.

FXU:  PMCR[20:23], 4-bit code selecting FXU source event set.

ICU:  PMCR[24:27], 4-bit code selecting ICU source event set.

SCU:  PMCR[28:31], 4-bit Code selecting SCU source event set.

      Events in a multichip processor are counted with hardware
counters and the selection of events as well as the control of the
counters is programmable via software.  The scheme provides the
capability to monitor many performance parameters with a minimal
number of hardware signals between the various processor chips.  A
special purpose monitor register contained in the Fixed Point Unit
(FXU) provides the capability to measure the number of times any
class of instruction is executed and provides the capability for
software to set an event such as run state or wait state that can be
directly counted by the monitor with the full...