Browse Prior Art Database

Test Methods for Logic Cell Array Designs

IP.com Disclosure Number: IPCOM000112224D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 108K

Publishing Venue

IBM

Related People

Galella, JW: AUTHOR [+2]

Abstract

A method is described for improving board level testing of designs that are based upon Logic Cell Array (LCA) technologies.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Test Methods for Logic Cell Array Designs

      A method is described for improving board level testing of
designs that are based upon Logic Cell Array (LCA) technologies.

      Field Programmable Gate Arrays (FPGAs) are high density user
programmable logic devices.  These FPGAs can be used as a low
development cost alternative to industry standard custom logic
circuits.  A benefit of FPGAs over industry standard custom logic
circuits is that the FPGA can be updated with a new design in a few
hours versus weeks for industry standard custom logic circuits.

      One type of FPGA is the LCA, which can be considered as a large
programmable logic device with similar architecture to a gate array.

The LCA family is loaded with its programming information after power
on reset from an external source.  The load mechanism allows for
master/slave devices during the programming sequence.

      The initial load of the LCA can occur via several methods,
which include serial bit stream or parallel loading from an external
Programmable Read Only Memory (PROM) or via microprocessor control.
There is a defined sequence of events and handshakes to inform the
system that the LCA load has been completed.

      Testing an assembled circuit card is an important part of the
manufacturing process.  All components on the card must be tested to
insure the quality and repeatability of the manufacturing process.
The problem to be addressed is how to improve the testing of the LCA
devices on a circuit card.  Functional testing may determine if the
LCA is operational with a high degree of confidence.  This type of
testing verifies the card and system under normal operating
conditions, i.e., running diagnostics, however, the functional test
method is a time consuming test.

      A preferred test is to use an in-circuit test (ICT) to verify
the LCA devices earlier in the manufacturing test cycle.  Since the
ICT is a much shorter test than the functional test, the overall
cycle time of the test process is reduced.

As indicated in the Figure, the typical load sequence occurs as
follows:

1.  Power on reset occurs.

2.  A master LCA drives a configuration clock (CCLK) to a serial PROM
    and all LCA slaves.

3.  The serial PROM provides the serial programming data to the data
    in (DIN) pin on the master LCA.

4.  One clock (CCLK) pulse after receiving the serial data in (DIN)
    the LCA master drives the serial data out (DOUT) to a first LCA
    slave 1 in a programming chain.

5.  The first LCA slave 1 receives the data on its DIN pin.

6.  One clock pulse after receiving the serial data in (DIN) the
    first LCA slave 1 drives the serial data out (DOUT) to the next
    LCA slave (not shown) in the programming chain.

7.  This sequence continues to all LCA slave devices in the
  ...