Browse Prior Art Database

Efficient Method of Generating Two Phase Non-Overlapping Clocks

IP.com Disclosure Number: IPCOM000112227D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 99K

Publishing Venue

IBM

Related People

Chan, JC: AUTHOR

Abstract

A new method of generating a two phase, non-overlapping a single phase clock using discrete logic is presented. The design is logically hazard free and easily testable. This prevents the race condition and other timing hazards in sequential logic by using an LSSD design methodology.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Efficient Method of Generating Two Phase Non-Overlapping Clocks

      A new method of generating a two phase, non-overlapping a
single phase clock using discrete logic is presented.  The design is
logically hazard free and easily testable.  This prevents the race
condition and other timing hazards in sequential logic by using an
LSSD design methodology.

      Traditionally, sequential logic design is based on an edge
triggered flip flop operating in one phase clock mode.  While such an
approach is convenient from the design point of view, two drawbacks
exist.  First, extra hardware is required for the edge triggering
mechanism.  Second, sequential networks constructed with an edge
trigger are very difficult or impossible to test, especially when the
fault occurs within the flip flop.  To deal with these problems, IBM
developed the logic design methodology of Level Sensitive Scan Design
(LSSD) in the early 1970's.  Essential to this approach is the Shift
Register Latch (SRL) that allows the state of the sequential logic to
be controlled directly by means of a scan chain.  To achieve race
free operation, the level sensitive attribute of LSSD networks
requires the use of a two phase, non-overlapping clocking scheme.
From a designer's point of view, traditional design of sequential
logic in a single phase clocking scheme must be met with LSSD by a
two phase clock operation.  A scheme of bridging this conversion of
the clock generation is presented in this disclosure.  Figure 2.
Clocking Mechanism in LSSD Sequential Network.

      The clocking scheme of traditional sequential logic design is
illustrated in Fig. 1.  Here, all memory storage devices within the
network are implemented in the form of edge triggered flip flops.  To
overcome all the inherent race and timing hazards, a clock is used to
supervise the operation in a locked step manner by synchronizing the
transition of states.  The transitions are usually triggered by
either the rising or falling edge of the clock.  Thus, the frequency
of the clock determines the speed upon which the network can operate
properly.  In LSSD networks, the corresponding set of clocking
mechanisms in two phase mode is illustrated in Fig. 2, with the
duration of the non-overlapping period shown.  Here, the 'A' and 'B'
clocks are derived...