Browse Prior Art Database

RISC Superscalar Pipeline Out-of-Order Statistics Gathering and Analysis

IP.com Disclosure Number: IPCOM000112228D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 135K

Publishing Venue

IBM

Related People

Gariazzo, RE: AUTHOR [+2]

Abstract

The RISC Superscalar Pipeline Out-of-Order Statistics Gathering and Analysis was developed to better understand and improve the performance of the Graphics Floating Point Engine.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 43% of the total text.

RISC Superscalar Pipeline Out-of-Order Statistics Gathering and Analysis

      The RISC Superscalar Pipeline Out-of-Order Statistics Gathering
and Analysis was developed to better understand  and improve the
performance of the Graphics Floating Point Engine.

      The Graphics Floating Point Engine (GFPE), is a superscalar
microprocessor based on the RISC System/6000* Power PC architecture,
used in graphics and Multimedia applications.  It is a single chip
implementation that contains an Instruction cache, a Data cache, a
Branch Processor, a Superscalar Unit, two Fixed Point Units, two Load
Store Units, and three Floating Point Units.

      If a RISC Superscalar pipeline has the capacity of executing
instructions in a different order than the order in which the
instructions were received, it poses the 'out-of-order execution'
capability.  This improves the performance of the pipeline by
optimizing its usage throughout the instruction paths.  The
'out-of-order execution' allows the pipeline to continue the
processing of instructions even if instructions sequentially ahead of
them can not be completed.  In this manner, stage idle cycles are
minimized.

      Studying the 'out-of-order execution' implementation is
impossible without the help of automated tools.  The difficulty
arises from the fact that every completed instruction has to be
positioned in relation to the surrounding completed instructions in
multiple stages.  Once the instruction has been located, a comparison
should be done with other instructions to determine if it has been
completed out-of-order from the original sequence.  This endeavor not
only has to be carried out for every cycle, but also across cycles.

The complexity increases with the size of the instruction trace to be
studied.

      This disclosure describes a system designed to monitor the
superscalar pipeline instruction processing in real time.  As the
instructions are completed, they are analyzed for their sequential
order compared to their original order.  The resulting data is
accumulated until the whole instruction trace is done.  This tool is
attached to the GFPE TIMER MODEL.

      Advantages - The intention is to provide an automated tool to
study the characteristics of this RISC Superscalar Pipeline
implementation.

      The RISC Superscalar Pipeline Out-of-Order Statistics Gathering
and Analysis tool is an attachment to the Graphics Floating Point
Engine processor TIMER MODEL.  It works in conjunction with the GFPE
TIMER to gather information on the sequence of the instructions
processed by the pipeline model:  it knows in which order the
instructions were received, and it test for each instruction comple
tion.  Once these two pieces of information are known, then tool runs
an analysis utility searching for out-of-order execution.

An overview of the system implemented is given in the Figure.

      Since the interest is on instructions processed by the
pipe...