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Dense High Performance Cell for Multiport Applications

IP.com Disclosure Number: IPCOM000112263D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 64K

Publishing Venue

IBM

Related People

Buettner, S: AUTHOR [+3]

Abstract

Disclosed is a memory in which the internal nodes of the memory cell are connected to the gates of the read device transistors. The cell selection is carried out with a restored select line, driven by an n-type device of a word line driver. Due to the small cell load of the read device transistor gate, this approach allows the usage of dual rail sensing and is particularly suitable for multiport applications.

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Dense High Performance Cell for Multiport Applications

      Disclosed is a memory in which the internal nodes of the memory
cell are connected to the gates of the read device transistors.  The
cell selection is carried out with a restored select line, driven by
an n-type device of a word line driver.  Due to the small cell load
of the read device transistor gate, this approach allows the usage of
dual rail sensing and is particularly suitable for multiport
applications.

      Fig. 1 shows a prior art three port cell.  Here the internal
latch (T1...T4) is single ended and is written by the wordline write
signal (WLW) and the data at the DI line.

      In a read operation, an isolation inverter (T6.T7) is required
in order to avoid cell interaction with the bitline potential.  A
single ended bitline is used, i.e.  the cell inverter has to drive
either the bitline up or down requiring a power supply swing.  The
data out stage is a simple inverter with pull-up device for
recovering the (VDD-Vt) bitline uplevel which is the maximum voltage
level obtained via devices T6 and T8.

      In this approach, the bitline will always be charged and
discharged by two devices in series and a full swing is required.
Thus large transistors T6...T9 are required in order to obtain good
performance.  The penalty paid for these large devices is an increase
in the cell area.

      Fig. 2 shows the disclosed memory scheme.  Very small devices
are connected with the...