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Browse Prior Art Database

Central Queuing Element for a Single Chip RISC Microprocessor

IP.com Disclosure Number: IPCOM000112264D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Barrera, D: AUTHOR [+2]

Abstract

Disclosed is a reduced hardware solution for queuing of instruction store data, instruction fetch data, and instruction load data. The queuing device is used in a microprocessor utilizing a store-through-mixed instruction and data cache. Described is a central queuing device (multi-ported Random Access Memory (RAM)) which holds queued data. This device is loaded from four sources and may be accessed by five sinking devices. Through the use of the central queuing device about a 50% logic reduction is achieved. This is due to the compact nature of the multi-ported RAM verses general hardware latches.

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This is the abbreviated version, containing approximately 52% of the total text.

Central Queuing Element for a Single Chip RISC Microprocessor

      Disclosed is a reduced hardware solution for queuing  of
instruction store data, instruction fetch data, and instruction load
data.  The queuing device is used  in a microprocessor utilizing a
store-through-mixed instruction and data cache.  Described is a
central queuing device (multi-ported Random Access Memory (RAM))
which holds queued data.  This device is loaded from four sources and
may be accessed by five sinking devices.  Through the use of the
central queuing device about a 50% logic reduction is achieved.  This
is due to the compact nature of the multi-ported RAM verses general
hardware latches.

      The central queuing device receives data from four different
sources:  The first source of data is from memory.  The memory data
is gathered in the central queuing device to formulate a cache block
(reload buffer) which is then written into the cache.  The memory
data is also merged with store data to formulate merged write data
which is sent back to memory (read-modify-write process).  The second
source of data to the central queuing device is store data which is
generated from store instructions being executed.  Several pieces of
store data are queued waiting output to memory.  The third source of
data is from the cache.  The cache data is merged with the store data
to form memory/cache write data (read-modify-write process) which is
subsequently queued and written back to the memory/cache.  Also, the
cache data is saved into the central queuing device during fetch
cache read operations forsubsequent instruction supply to the
instruction queue.  The fourth source of data into the central
queuing device is the central queuing device itself.  To f...