Browse Prior Art Database

Decode-Save Register

IP.com Disclosure Number: IPCOM000112265D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Muhich, JS: AUTHOR [+2]

Abstract

Disclosed is a method for reducing the cycle-time of pipelined microprocessors. In pipelined processors, there is a standard timing problem caused by stalls occuring at the lower stages. For example, if there is a stall at stage 0 (the lowest stage) then this information must be used to genereate hold equations at all stages above that stage. This serial hold logic can fundementally limit the cycle-time of a highly pipelined processor.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 59% of the total text.

Decode-Save Register

      Disclosed is a method for reducing the cycle-time of pipelined
microprocessors.  In pipelined processors, there is a standard timing
problem caused by stalls occuring at the lower stages.  For example,
if there is a stall at stage 0 (the lowest stage) then this
information must be used to genereate hold equations at all stages
above that stage.  This serial hold logic can fundementally limit the
cycle-time of a highly pipelined processor.

      An extra pipeline element in the pipeline can be used to break
the serial chain of logic associated with holding the pipeline.  This
stage, refered to as the decode-save stage can be placed at any point
in the pipeline, and simply mirrors the stage below it when it is
loaded each cycle.  However, if a hold occurs below this stage, this
stage is not held (nor are the stages above it).  Thus on the cycle
in which a hold occurs in the pipeline below the decode-save stage,
the decode-save register is advanced, but its mirror stage is held.
On the cycle after the hold, the decode-save stage and the stages
above the decode-save stage are held.  Note that the hold term for
the higher stages is now available at a latch output instead of near
the end of the cycle.  When the hold on the stage below decode- save
is released, it is loaded with the information at decode-save (the
decode-save stage is still held), and the two stages are synchronized
again.

      Following is an example usage of this...