Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Request in Logic

IP.com Disclosure Number: IPCOM000112272D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 132K

Publishing Venue

IBM

Related People

Beardsley, BC: AUTHOR [+2]

Abstract

To support 32 logical channels per path it was necessary to improve the performance of the "Request In" function on the 3990. The "Request In" function was moved to hardware to support the improved performance and to free up the microcode interaction to support this function. The following elements make up the hardware management of the "Request In" function.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

Request in Logic

      To support 32 logical channels per path it was necessary to
improve the performance of the "Request In" function on the 3990.
The "Request In" function was moved to hardware to support the
improved performance and to free up the microcode interaction to
support this function.  The following elements make up the hardware
management of the "Request In" function.

1.  Request In Registers

2.  Degate functions performed on these Request In registers

3.  Logical Path Table

4.  Inhibit Vectors

5.  Rotational Priority Logic

      See Fig. 1 for the layout of the Request In logic.  After the
storage path updates the Request In register the hardware will start
processing that Request In.  It first looks to see whether any degate
function is activated.  If not it will further compute whether it is
a dynamic or status Request In.  After resolving that it will
arbitrate among all the Request Ins to ensure the one with the
highest priority is selected.  After determining the logical path the
hardware will read out the corresponding out serial address.

      Request In Registers - The Request In registers consist of four
types of registers indicating different types of "Request In"
information.  An additional Dynamic Request In register was added to
provide a distinction from the storage path's perspective of a high
(dynamic) priority versus a low (static) priority "Request In".

1.  Static Unsuppressible

2.  CUE Owed

3.  Static Suppressible

4.  Dynamic Unsuppressible

      Degate Functions - The "Request In" function is degated by
certain conditions associated with the storage path.  There are two
levels of degation:  one degates all of the "Request Ins"; another
will degate only an individual channel's "Request In".  Some of the
conditions that will cause a degate of all the "Request In" are the
following:

1.  Storage Path Processor stopped

2.  Storage Path Locked and Selected

3.  Storage Path Fenced

4.  Storage Path Locked and Long Select Active

      The storage path also has a register which can individually
degate a logical channel.

      Logical Path Table - There is a logical path table that
contains one entry per logical channel.  It is updated whenever a
logical path is established or removed.  Each entry consists of:

o   The 16 bit serial link address for that logical path.

o   A 4 bit vecter indicating whether the logical path is valid
    (established) and if established for which associated physical
    link.

o   A bit indicating whether the channel is a RECAP channel or not.

      Inhibit Vectors - There is an ESCON architecture requirement
that a request connection to a logical path cannot be retransmitted
for at least 50 microseconds after the request has been refused.  The
hardware will manage a 32 bit inhibit vector which will keep track of
each individual channel to prevent the hardware from requesting a
reconnection to the same logical path mo...