Browse Prior Art Database

Translation Lookaside Buffer Cycle Stealing

IP.com Disclosure Number: IPCOM000112274D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Moore, CR: AUTHOR [+3]

Abstract

Disclosed is a method for reducing the latency for reloading the translation mechanism of an instructuction fetch unit from a unified Memory Management Unit (MMU) structure. This method is useful for processors which have a main MMU which handles both data and instruction translation, but which also contain a smaller instruction- only MMU which relies on the main MMU to reload translation objects.

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This is the abbreviated version, containing approximately 73% of the total text.

Translation Lookaside Buffer Cycle Stealing

      Disclosed is a method for reducing the latency for reloading
the translation mechanism of an instructuction fetch unit from a
unified Memory Management Unit (MMU) structure.  This method is
useful for processors which have a main MMU which handles both data
and instruction translation, but which also contain a smaller
instruction- only MMU which relies on the main MMU to reload
translation objects.

      In low-end microprocessors, silicon area is at a premium, and
therefor must be used with the greatest efficiency possible (not
necessarily the greatest performance possible).  As a result unified
caches and TLB structures typically make sense, because a single
larger unified cache will normally give better hit rates than two
smaller ones which use the same total area.  The result is the need
to arbitrate between instruction accesses and data accesses

(multiported arrays are also expensive area-wise).  This is fairly
easy for unified caches because there are no major synchronization
issues to deal with (the same software protocol which is required to
synchronize separate instruction and data caches works for a unified
cache).  However, the TLB structure has synchronization requirements
in the hardware that must be met in order to arbitrate it.

      There are two major synchronization issues with a unified TLB:
TLB reloading (caused by a TLB miss) and TLB invalidation (caused by
a TLB invalidate instruction...