Browse Prior Art Database

Graphics Assists using Pipelined Stores and No-Disconnect Loads

IP.com Disclosure Number: IPCOM000112282D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 175K

Publishing Venue

IBM

Related People

Feiste, KA: AUTHOR [+2]

Abstract

Disclosed is a scheme to efficiently move data from a Central Processing Unit (CPU) to a graphics adapter. This scheme provides a pipelined Store fast-release mechanism in which a stream of data (up to 128 bytes) is sent from the CPU to a graphics adapter and as soon as the data is unloaded from the CPU General Purpose Registers (GPRs) onto the processor bus (PBUS) then the CPU is released to continue executing the next instruction. In addition, a Load with no disconnect feature prevents any other I/O activity, including DMA and I/O interrupts, from occuring during Load instructions to the graphics adapter.

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This is the abbreviated version, containing approximately 52% of the total text.

Graphics Assists using Pipelined Stores and No-Disconnect Loads

      Disclosed is a scheme to efficiently move data from a Central
Processing Unit (CPU) to a graphics adapter.  This scheme provides a
pipelined Store fast-release mechanism in which a stream of data (up
to 128 bytes) is sent from the CPU to a graphics adapter and as soon
as the data is unloaded from the CPU General Purpose Registers (GPRs)
onto the processor bus (PBUS) then the CPU is released to continue
executing the next instruction.  In addition, a Load with no
disconnect feature prevents any other I/O activity, including DMA and
I/O interrupts, from occuring during Load instructions to the
graphics adapter.

      Fig. 1 shows a system diagram consisting of a multi-chip
super-scalar RISC CPU, memory, and I/O control units.  The CPU
consists of an Instruction Cache Unit (ICU), a Fixed Point Unit
(FXU), a Floating Point Unit (FPU), four Data Cache Units (DCU), and
a Storage Control Unit (SCU).  Graphics adapters are connected to the
CPU via a Graphics I/O (GIO) control unit which has a dedicated
Graphics Bus.  Graphics computations are made in the FXU and FPU
units, and the data is moved to the GIO graphics bus via the SCU chip
and System I/O (SIO) bus.

      Fig. 2 shows the PIO Load/Store logic in the SCU chip.  Data is
loaded into a 256 byte buffer in the SCU via either the PBUS or SIO
bus for loads and stores.  This buffer is large enough to hold two
sets of 32 X 4 byte GPR registers from the FXU.  The SCU receives the
load/store instruction command on the PBUS control bus and responds
back to load/stores on the same bus.  These commands are decoded by
the command decoder.  In addition a unique bus unit ID passed with
the address on the data bus is decoded with the command to identify
which bus unit will receive the command.  The PIO control logic
controls the flow of data into and out of the buffer using the read
and write pointers.  Data can be unloaded from the buffer at the same
time that it is being loaded.  Fig. 3 shows two back to back Store
Fast release operations which move 16 bytes of data.  As seen in the
Figure, the Store instruction is sent from the FXU to SCU over the
PB...