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External Test System AC-Improvement

IP.com Disclosure Number: IPCOM000112298D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 8 page(s) / 196K

Publishing Venue

IBM

Related People

Diebold, U: AUTHOR [+8]

Abstract

Older types of semiconductor test systems and sometimes cost-effective tester products are very poor in their AC capabilities (rise and fall times, pulse width) due to the slow signal drivers within the pin electronics (PEC). This problem results in a limited employment of these test systems for characterization and manufacturing test of current products. The solution for this problem is to improve the signal driver capabilities using an AC-Extension outside the test system on the performance board which is adapted to the device under test (DUT). With this AC-Improvement the test system reaches a higher performance class without modifications to the tester.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 37% of the total text.

External Test System AC-Improvement

      Older types of semiconductor test systems and sometimes
cost-effective tester products are very poor in their AC capabilities
(rise and fall times, pulse width) due to the slow signal drivers
within the pin electronics (PEC).  This problem results in a limited
employment of these test systems for characterization and
manufacturing test of current products.  The solution for this
problem is to improve the signal driver capabilities using an
AC-Extension outside the test system on the performance board which
is adapted to the device under test (DUT).  With this AC-Improvement
the test system reaches a higher performance class without
modifications to the tester.

      Prior Art - On test systems with limited AC-capabilities the
problem arises that the increased test requirements to achieve the
necessary AC-test coverage on current products can not be
accomplished.  The limited AC-capabilities are a result of the 'slow'
pin electronics within the front ends of these test systems.  There,
the long rise and fall times of the signal drivers do not allow the
programming of short pulses.  However, short pulses with exact edge
positioning are the basis to generate an aggressive timing which is
essential to achieve the increased quality requirements for the test
of current products.

      The resulting flat signal slopes due to the long rise and fall
times (Fig. 1, 6ns with contacted DUT) are the reason that short
pulses cannot reach the defined uplevel (Fig. 1, 3.8V) within the
programmed pulse width.  The internal, digital electronic of the
tester, however, is capable of generating these short pulses.  In
comparison to this, a long pulse (Fig. 1, 10ns) will reach the
defined uplevel.

      A further problem of these flat slopes is that during tight
pulse sequences of different signals (mostly DUT clock pins) it is
not possible to get a sufficient signal gap.  The overlapping of the
pulses leads to flush conditions and logic failures as shown in Fig.
2.

      A further problem of the poor drive capability is the
inaccuracy during a test with tight timings.  Due to the physical
attributes of DUT receivers which depend on design (TTL, CMOS, etc.)
as well as the influence of process variations during manufacturing,
the threshold of the receivers is unstable.  Most of the time
hysteresis has to be taken into account.  During the calibration of
the test system, the timing will normally not be adjusted to the
exact receiver threshold but to the 50% point between the defined
signal up and down levels (Fig. 3).

      In the case that the receiver threshold does not match the
signal level used for calibration, a deviation between the program
defined timing and the actual timing within the product occurs (Fig.
4a).

If the test system produces steeper slopes this problem can be
minimized (Fig. 4b).

      On some products receivers with dynamic characteristics are
used.  Thi...