Browse Prior Art Database

Renaming of an Instruction Register Field for Speed Improvement

IP.com Disclosure Number: IPCOM000112301D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Karim, FO: AUTHOR [+2]

Abstract

Instruction decode in hardware logic always presents challenges to minimizing the cycle time of a processor. The need to encode more information into an instruction's fixed bit length presents a conflicting goal to minimizing decode time. For example, in the RISC System/6000* instruction set architecture, several instructions make use of a field denoted by RA|0. For these instructions, the execution unit is to use the contents of register RA as an operand for the instruction, however, if the RA field is zero, then the value of zero is used instead. This requires additional logic to decide if RA is a register address to be used to read a register file, or, if some constant data value (in this case zero) is to be substituted instead.

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Renaming of an Instruction Register Field for Speed Improvement

      Instruction decode in hardware logic always presents challenges
to minimizing the cycle time of a processor.  The need to encode more
information into an instruction's fixed bit length presents a
conflicting goal to minimizing decode time.  For example, in the RISC
System/6000* instruction set architecture, several instructions make
use of a field denoted by RA|0.  For these instructions, the
execution unit is to use the contents of register RA as an operand
for the instruction, however, if the RA field is zero, then the value
of zero is used instead.  This requires additional logic to decide if
RA is a register address to be used to read a register file, or, if
some constant data value (in this case zero) is to be substituted
instead.

      In Fig. 1 is a diagram of part of a typical processor pipeline
including a rename stage and an execution unit stage.  The rename
stage essentially translates architected register addresses to
physical register addresses.  These renamed register addresses are
then passed on to the execution unit in the form of a "control word".
Here the RA|0 field is decoded and a signal is generated which
controls the multiplexor.  The multiplexor selects either the output
of the constant generator (zero) or the value read from the register
file (RA).  The operand data from the multiplexor is then fed to the
next stage of the execution unit.  The decode and selection logic
shown add directly to the total cycle time of the execution unit.
Since execution unit cycle times are often in the most critical paths
of processor designs, it is desirable to eliminate this added delay.
A method for doing this follows.

      A mechanism which eliminates this delay from the execution unit
is shown in Fig. 2. ...