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Integrated Loop Filter for Phase Lock Loop

IP.com Disclosure Number: IPCOM000112302D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Coburn, RL: AUTHOR [+3]

Abstract

Disclosed is a practical method to integrate the final element of the Phased Lock Loop (PLL), the Loop Filter, by digital means. A problem with a digital implementation of the loop filter is that it must be a second order filter to stabilize a PLL. Typically, digital filters are large and complex to design to the second order requirement.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 64% of the total text.

Integrated Loop Filter for Phase Lock Loop

      Disclosed is a practical method to integrate the final element
of the Phased Lock Loop (PLL), the Loop Filter, by digital means.  A
problem with a digital implementation of the loop filter is that it
must be a second order filter to stabilize a PLL.  Typically, digital
filters are large and complex to design to the second order
requirement.

      The algorithm shown describes a set of simple operations that
form an approximation to the typical second order filter having the
impedance:

                   < S + 1 over < R1 (C1+C2) >> over

                   < S ( < S+ 1 over < R1 C1 > > ) >

      The use of two separate counters is required to achieve a
second order response, and is analogous to the use of two energy
storage elements (C1 and C2) in a linear analog loop filter.  The
clock frequency that drives the filter, the counter size (number of
bits) for CT1, and the counter size for CT2, must be chosen to
provide the desired transfer function; i.e., the equivalent R1, C1,
and C2.

      Since the implementation is digital, noise sensitivity to
ground at the filter is eliminated because the filter is not external
and has no analog voltages.

      The inputs for each clock cycle are the two single bit signals
UP and DOWN.  The output to the system is the register OUT.  The two
internal counters that must be preserved from one cycle to the next
are the counters C...