Browse Prior Art Database

High Performance L1 Data Cache Power Management

IP.com Disclosure Number: IPCOM000112316D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Braceras, GM: AUTHOR [+3]

Abstract

The increasing performance of RISC processors is placing larger demands on L1 Data cache performance. To achieve these goals the L1 Data cache power is going up exponentially. The L1 Data cache has become the number 1 power consumer in the processor complex. This places increased strains on the system power and cooling requirements. This results in higher operating temperatures which means higher chip junction temperatures translating directly into a loss of performance. This invention implemented on a RISC System/6000* processor offers a solution to this problem.

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High Performance L1 Data Cache Power Management

      The increasing performance of RISC processors is placing larger
demands on L1 Data cache performance.  To achieve these goals the L1
Data cache power is going up exponentially.  The L1 Data cache has
become the number 1 power consumer in the processor complex.  This
places increased strains on the system power and cooling
requirements.  This results in higher operating temperatures which
means higher chip junction temperatures translating directly into a
loss of performance.  This invention implemented on a RISC
System/6000* processor offers a solution to this problem.

      To increase L1 Data cache performance, designs are supporting
larger Data cache line sizes with increased associativity and greatly
reduced cycle times.  This drives the power requirements up
exponentially.  The RISC System/6000 L1 Data cache draws 32 watts at
a 15 nanosecond cycle time when continuously powered on.  The
solution to this problem may be found by examining the array design
and the software application's utilization of the L1 Data cache.

      Since all high performance L1 Data cache designs are based on a
clocked array design the power may be controlled by simply blocking
the clock to the array.  When the clock is inhibited to the array the
power requirement will drop to zero.  The design of the array will
allow for the clock to be gated on a cycle to cycle basis therefore
giving an instant on and off capability.

      With clock gating in place the power of the L1 Data cache is a
function of the software application's utilization of the L1 Data
cache.  The following equation is used to calculate L1 Data cache
utilization.

    (#load-store + DCmiss*Cycles_A + TLBmiss*Cycles_B)/CPI

 Definitions

  #load-store - The number of load and store references in an
                   application per instruction.  (The L1 Data cache
is
                   required for 1 cycle per load or store reference.)...