Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Special Modes for Processor Bring-up

IP.com Disclosure Number: IPCOM000112321D
Original Publication Date: 1994-Apr-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Balser, DM: AUTHOR [+4]

Abstract

Disclosed is a hardware method for running a microprocessor in eight different modes. The modes are selected to aid in evaluating software debug, hardware debug, and testing of initial hardware. These modes provide a useful environment for testing and isolation of errors at the cost of a small amount of additional hardware complexity.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Special Modes for Processor Bring-up

      Disclosed is a hardware method for running a microprocessor in
eight different modes.  The modes are selected to aid in evaluating
software debug, hardware debug, and testing of initial hardware.
These modes provide a useful environment for testing and isolation of
errors at the cost of a small amount of additional hardware
complexity.

      Three state bits define the eight modes in which the processor
runs.  The Branch Mode (BM), the Address Compare (AC), and the Wait
for Quiesce (WQ) bits.  When the Branch Mode bit is inactive, the
processor's instruction prefetch unit dispatches instructions to all
of its execution units in parallel, therefore aiding in maximum
execution and performance (normal run mode).  When the Branch Mode
bit is active, the instruction prefetch unit dispatches instructions
in a serial fashion to the execution units which allows a break point
between each and every instruction.  When the Address Compare bit is
inactive the processor is not halted (normal run mode).  Activating
the Address Compare bit causes instruction addresses to be compared
with a register address and if they match to halt the processor at
that point in the instruction processing.  The Wait for Quiesce bit
determines whether all dispatched instructions will be completed
prior to stopping the clocks or whether the clocks are immediately
stopped when a request to halt the processor is received via the
Address Compare.

      When all modes bits are inactive, the processor runs at a
normal execution speed.  With just the WQ bit active, the processor
runs in a nonpipelined maner, only dispatching one instruction at a
time and waiting until that instruction is finished before starting
the next instruction.  This mode is called NONOVERLAP EXECUTION.
When the...